Config.in 12 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. choice
  13. prompt "Target Architecture"
  14. default BR2_i386
  15. help
  16. Select the target architecture family to build for.
  17. config BR2_arcle
  18. bool "ARC (little endian)"
  19. select BR2_ARCH_HAS_MMU_MANDATORY
  20. help
  21. Synopsys' DesignWare ARC Processor Cores are a family of
  22. 32-bit CPUs that can be used from deeply embedded to high
  23. performance host applications. Little endian.
  24. config BR2_arceb
  25. bool "ARC (big endian)"
  26. select BR2_ARCH_HAS_MMU_MANDATORY
  27. help
  28. Synopsys' DesignWare ARC Processor Cores are a family of
  29. 32-bit CPUs that can be used from deeply embedded to high
  30. performance host applications. Big endian.
  31. config BR2_arm
  32. bool "ARM (little endian)"
  33. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  34. help
  35. ARM is a 32-bit reduced instruction set computer (RISC)
  36. instruction set architecture (ISA) developed by ARM Holdings.
  37. Little endian.
  38. http://www.arm.com/
  39. http://en.wikipedia.org/wiki/ARM
  40. config BR2_armeb
  41. bool "ARM (big endian)"
  42. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  43. help
  44. ARM is a 32-bit reduced instruction set computer (RISC)
  45. instruction set architecture (ISA) developed by ARM Holdings.
  46. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. select BR2_ARCH_HAS_MMU_MANDATORY
  53. help
  54. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  55. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  56. http://en.wikipedia.org/wiki/ARM
  57. config BR2_aarch64_be
  58. bool "AArch64 (big endian)"
  59. select BR2_ARCH_IS_64
  60. select BR2_ARCH_HAS_MMU_MANDATORY
  61. help
  62. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  63. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  64. http://en.wikipedia.org/wiki/ARM
  65. config BR2_csky
  66. bool "csky"
  67. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  68. select BR2_ARCH_HAS_MMU_MANDATORY
  69. # Most variants are supported by gcc-9+, except one that is
  70. # handled as a special exception in package/gcc/Config.in.host
  71. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  72. help
  73. csky is processor IP from china.
  74. http://www.c-sky.com/
  75. http://www.github.com/c-sky
  76. config BR2_i386
  77. bool "i386"
  78. select BR2_ARCH_HAS_MMU_MANDATORY
  79. help
  80. Intel i386 architecture compatible microprocessor
  81. http://en.wikipedia.org/wiki/I386
  82. config BR2_m68k
  83. bool "m68k"
  84. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  85. help
  86. Motorola 68000 family microprocessor
  87. http://en.wikipedia.org/wiki/M68k
  88. config BR2_microblazeel
  89. bool "Microblaze AXI (little endian)"
  90. select BR2_ARCH_HAS_MMU_MANDATORY
  91. help
  92. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
  93. bus based architecture (little endian)
  94. http://www.xilinx.com
  95. http://en.wikipedia.org/wiki/Microblaze
  96. config BR2_microblazebe
  97. bool "Microblaze non-AXI (big endian)"
  98. select BR2_ARCH_HAS_MMU_MANDATORY
  99. help
  100. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
  101. bus based architecture (non-AXI, big endian)
  102. http://www.xilinx.com
  103. http://en.wikipedia.org/wiki/Microblaze
  104. config BR2_mips
  105. bool "MIPS (big endian)"
  106. select BR2_ARCH_HAS_MMU_MANDATORY
  107. help
  108. MIPS is a RISC microprocessor from MIPS Technologies. Big
  109. endian.
  110. http://www.mips.com/
  111. http://en.wikipedia.org/wiki/MIPS_Technologies
  112. config BR2_mipsel
  113. bool "MIPS (little endian)"
  114. select BR2_ARCH_HAS_MMU_MANDATORY
  115. help
  116. MIPS is a RISC microprocessor from MIPS Technologies. Little
  117. endian.
  118. http://www.mips.com/
  119. http://en.wikipedia.org/wiki/MIPS_Technologies
  120. config BR2_mips64
  121. bool "MIPS64 (big endian)"
  122. select BR2_ARCH_IS_64
  123. select BR2_ARCH_HAS_MMU_MANDATORY
  124. help
  125. MIPS is a RISC microprocessor from MIPS Technologies. Big
  126. endian.
  127. http://www.mips.com/
  128. http://en.wikipedia.org/wiki/MIPS_Technologies
  129. config BR2_mips64el
  130. bool "MIPS64 (little endian)"
  131. select BR2_ARCH_IS_64
  132. select BR2_ARCH_HAS_MMU_MANDATORY
  133. help
  134. MIPS is a RISC microprocessor from MIPS Technologies. Little
  135. endian.
  136. http://www.mips.com/
  137. http://en.wikipedia.org/wiki/MIPS_Technologies
  138. config BR2_nds32
  139. bool "nds32"
  140. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  141. select BR2_ARCH_HAS_MMU_MANDATORY
  142. help
  143. nds32 is a 32-bit architecture developed by Andes Technology.
  144. https://en.wikipedia.org/wiki/Andes_Technology
  145. config BR2_nios2
  146. bool "Nios II"
  147. select BR2_ARCH_HAS_MMU_MANDATORY
  148. help
  149. Nios II is a soft core processor from Altera Corporation.
  150. http://www.altera.com/
  151. http://en.wikipedia.org/wiki/Nios_II
  152. config BR2_or1k
  153. bool "OpenRISC"
  154. select BR2_ARCH_HAS_MMU_MANDATORY
  155. help
  156. OpenRISC is a free and open processor for embedded system.
  157. http://openrisc.io
  158. config BR2_powerpc
  159. bool "PowerPC"
  160. select BR2_ARCH_HAS_MMU_MANDATORY
  161. help
  162. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  163. alliance. Big endian.
  164. http://www.power.org/
  165. http://en.wikipedia.org/wiki/Powerpc
  166. config BR2_powerpc64
  167. bool "PowerPC64 (big endian)"
  168. select BR2_ARCH_IS_64
  169. select BR2_ARCH_HAS_MMU_MANDATORY
  170. help
  171. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  172. alliance. Big endian.
  173. http://www.power.org/
  174. http://en.wikipedia.org/wiki/Powerpc
  175. config BR2_powerpc64le
  176. bool "PowerPC64 (little endian)"
  177. select BR2_ARCH_IS_64
  178. select BR2_ARCH_HAS_MMU_MANDATORY
  179. help
  180. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  181. alliance. Little endian.
  182. http://www.power.org/
  183. http://en.wikipedia.org/wiki/Powerpc
  184. config BR2_riscv
  185. bool "RISCV"
  186. select BR2_ARCH_HAS_MMU_MANDATORY
  187. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  188. help
  189. RISC-V is an open, free Instruction Set Architecture created
  190. by the UC Berkeley Architecture Research group and supported
  191. and promoted by RISC-V Foundation.
  192. https://riscv.org/
  193. https://en.wikipedia.org/wiki/RISC-V
  194. config BR2_s390x
  195. bool "s390x"
  196. select BR2_ARCH_IS_64
  197. select BR2_ARCH_HAS_MMU_MANDATORY
  198. help
  199. s390x is a big-endian architecture made by IBM.
  200. http://www.ibm.com/
  201. http://en.wikipedia.org/wiki/IBM_System/390
  202. config BR2_sh
  203. bool "SuperH"
  204. select BR2_ARCH_HAS_MMU_OPTIONAL
  205. help
  206. SuperH (or SH) is a 32-bit reduced instruction set computer
  207. (RISC) instruction set architecture (ISA) developed by
  208. Hitachi.
  209. http://www.hitachi.com/
  210. http://en.wikipedia.org/wiki/SuperH
  211. config BR2_sparc
  212. bool "SPARC"
  213. select BR2_ARCH_HAS_MMU_MANDATORY
  214. help
  215. SPARC (from Scalable Processor Architecture) is a RISC
  216. instruction set architecture (ISA) developed by Sun
  217. Microsystems.
  218. http://www.oracle.com/sun
  219. http://en.wikipedia.org/wiki/Sparc
  220. config BR2_sparc64
  221. bool "SPARC64"
  222. select BR2_ARCH_IS_64
  223. select BR2_ARCH_HAS_MMU_MANDATORY
  224. help
  225. SPARC (from Scalable Processor Architecture) is a RISC
  226. instruction set architecture (ISA) developed by Sun
  227. Microsystems.
  228. http://www.oracle.com/sun
  229. http://en.wikipedia.org/wiki/Sparc
  230. config BR2_x86_64
  231. bool "x86_64"
  232. select BR2_ARCH_IS_64
  233. select BR2_ARCH_HAS_MMU_MANDATORY
  234. help
  235. x86-64 is an extension of the x86 instruction set (Intel i386
  236. architecture compatible microprocessor).
  237. http://en.wikipedia.org/wiki/X86_64
  238. config BR2_xtensa
  239. bool "Xtensa"
  240. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  241. help
  242. Xtensa is a Tensilica processor IP architecture.
  243. http://en.wikipedia.org/wiki/Xtensa
  244. http://www.tensilica.com/
  245. endchoice
  246. # For some architectures or specific cores, our internal toolchain
  247. # backend is not suitable (like, missing support in upstream gcc, or
  248. # no ChipCo fork exists...)
  249. config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  250. bool
  251. config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
  252. bool
  253. default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  254. # The following symbols are selected by the individual
  255. # Config.in.$ARCH files
  256. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  257. bool
  258. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  259. bool
  260. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  261. config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  262. bool
  263. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  264. config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  265. bool
  266. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  267. config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  268. bool
  269. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  270. config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  271. bool
  272. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  273. config BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  274. bool
  275. select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
  276. config BR2_ARCH_NEEDS_GCC_AT_LEAST_10
  277. bool
  278. select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
  279. config BR2_ARCH_NEEDS_GCC_AT_LEAST_11
  280. bool
  281. select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
  282. # The following string values are defined by the individual
  283. # Config.in.$ARCH files
  284. config BR2_ARCH
  285. string
  286. config BR2_ENDIAN
  287. string
  288. config BR2_GCC_TARGET_ARCH
  289. string
  290. config BR2_GCC_TARGET_ABI
  291. string
  292. config BR2_GCC_TARGET_NAN
  293. string
  294. config BR2_GCC_TARGET_FP32_MODE
  295. string
  296. config BR2_GCC_TARGET_CPU
  297. string
  298. # The value of this option will be passed as --with-fpu=<value> when
  299. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  300. # wrapper (external toolchain)
  301. config BR2_GCC_TARGET_FPU
  302. string
  303. # The value of this option will be passed as --with-float=<value> when
  304. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  305. # wrapper (external toolchain)
  306. config BR2_GCC_TARGET_FLOAT_ABI
  307. string
  308. # The value of this option will be passed as --with-mode=<value> when
  309. # building gcc (internal backend) or -m<value> in the toolchain
  310. # wrapper (external toolchain)
  311. config BR2_GCC_TARGET_MODE
  312. string
  313. # Must be selected by binary formats that support shared libraries.
  314. config BR2_BINFMT_SUPPORTS_SHARED
  315. bool
  316. # Must match the name of the architecture from readelf point of view,
  317. # i.e the "Machine:" field of readelf output. See get_machine_name()
  318. # in binutils/readelf.c for the list of possible values.
  319. config BR2_READELF_ARCH_NAME
  320. string
  321. # Set up target binary format
  322. choice
  323. prompt "Target Binary Format"
  324. default BR2_BINFMT_ELF if BR2_USE_MMU
  325. default BR2_BINFMT_FLAT
  326. config BR2_BINFMT_ELF
  327. bool "ELF"
  328. depends on BR2_USE_MMU
  329. select BR2_BINFMT_SUPPORTS_SHARED
  330. help
  331. ELF (Executable and Linkable Format) is a format for libraries
  332. and executables used across different architectures and
  333. operating systems.
  334. config BR2_BINFMT_FLAT
  335. bool "FLAT"
  336. depends on !BR2_USE_MMU
  337. help
  338. FLAT binary is a relatively simple and lightweight executable
  339. format based on the original a.out format. It is widely used
  340. in environment where no MMU is available.
  341. endchoice
  342. # Set up flat binary type
  343. choice
  344. prompt "FLAT Binary type"
  345. default BR2_BINFMT_FLAT_ONE
  346. depends on BR2_BINFMT_FLAT
  347. config BR2_BINFMT_FLAT_ONE
  348. bool "One memory region"
  349. help
  350. All segments are linked into one memory region.
  351. config BR2_BINFMT_FLAT_SHARED
  352. bool "Shared binary"
  353. depends on BR2_m68k
  354. # Even though this really generates shared binaries, there is no libdl
  355. # and dlopen() cannot be used. So packages that require shared
  356. # libraries cannot be built. Therefore, we don't select
  357. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  358. # Although this adds -static to the compilation, that's not a problem
  359. # because the -mid-shared-library option overrides it.
  360. help
  361. Allow to load and link indiviual FLAT binaries at run time.
  362. endchoice
  363. if BR2_arcle || BR2_arceb
  364. source "arch/Config.in.arc"
  365. endif
  366. if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
  367. source "arch/Config.in.arm"
  368. endif
  369. if BR2_csky
  370. source "arch/Config.in.csky"
  371. endif
  372. if BR2_m68k
  373. source "arch/Config.in.m68k"
  374. endif
  375. if BR2_microblazeel || BR2_microblazebe
  376. source "arch/Config.in.microblaze"
  377. endif
  378. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  379. source "arch/Config.in.mips"
  380. endif
  381. if BR2_nds32
  382. source "arch/Config.in.nds32"
  383. endif
  384. if BR2_nios2
  385. source "arch/Config.in.nios2"
  386. endif
  387. if BR2_or1k
  388. source "arch/Config.in.or1k"
  389. endif
  390. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  391. source "arch/Config.in.powerpc"
  392. endif
  393. if BR2_riscv
  394. source "arch/Config.in.riscv"
  395. endif
  396. if BR2_s390x
  397. source "arch/Config.in.s390x"
  398. endif
  399. if BR2_sh
  400. source "arch/Config.in.sh"
  401. endif
  402. if BR2_sparc || BR2_sparc64
  403. source "arch/Config.in.sparc"
  404. endif
  405. if BR2_i386 || BR2_x86_64
  406. source "arch/Config.in.x86"
  407. endif
  408. if BR2_xtensa
  409. source "arch/Config.in.xtensa"
  410. endif
  411. endmenu # Target options