osd32mp1-red.dts 12 KB

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  1. /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
  2. /*
  3. * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
  4. * Author: STM32CubeMX code generation for STMicroelectronics.
  5. */
  6. /* For more information on Device Tree configuration, please refer to
  7. * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
  8. */
  9. /dts-v1/;
  10. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  11. #include "stm32mp15-osd32mp1-ddr3-1x4Gb-1066-binG.dtsi"
  12. #include "stm32mp157c.dtsi"
  13. #include "stm32mp157cac-pinctrl.dtsi"
  14. #include "stm32mp15-ddr.dtsi"
  15. #include "stm32mp157c-security.dtsi"
  16. #include <dt-bindings/power/stm32mp1-power.h>
  17. / {
  18. model = "Octavo OSD32MP1-RED board";
  19. compatible = "octavo,osd32mp1-red", "st,stm32mp157";
  20. chosen {
  21. stdout-path = "serial0:115200n8";
  22. };
  23. aliases {
  24. serial0 = &uart4;
  25. serial1 = &usart3;
  26. serial2 = &uart7;
  27. gpio0 = &gpioa;
  28. gpio1 = &gpiob;
  29. gpio2 = &gpioc;
  30. gpio3 = &gpiod;
  31. gpio4 = &gpioe;
  32. gpio5 = &gpiof;
  33. gpio6 = &gpiog;
  34. gpio7 = &gpioh;
  35. gpio8 = &gpioi;
  36. gpio25 = &gpioz;
  37. i2c3 = &i2c4;
  38. };
  39. clocks {
  40. clk_lse: clk-lse {
  41. st,drive = < LSEDRV_MEDIUM_HIGH >;
  42. };
  43. clk_hse: clk-hse {
  44. st,digbypass;
  45. };
  46. };
  47. }; /*root*/
  48. &pinctrl {
  49. sdmmc1_pins_mx: sdmmc1_mx-0 {
  50. pins1 {
  51. pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
  52. <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
  53. <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
  54. <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
  55. <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
  56. bias-disable;
  57. drive-push-pull;
  58. slew-rate = <1>;
  59. };
  60. pins2 {
  61. pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
  62. bias-disable;
  63. drive-push-pull;
  64. slew-rate = <3>;
  65. };
  66. };
  67. sdmmc2_pins_mx: sdmmc2_mx-0 {
  68. pins1 {
  69. pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
  70. <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
  71. <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
  72. <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
  73. <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
  74. <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
  75. <STM32_PINMUX('C', 7, AF10)>, /* SDMMC2_D7 */
  76. <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
  77. <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
  78. bias-pull-up;
  79. drive-push-pull;
  80. slew-rate = <1>;
  81. };
  82. pins2 {
  83. pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
  84. bias-pull-up;
  85. drive-push-pull;
  86. slew-rate = <2>;
  87. };
  88. };
  89. sdmmc3_pins_mx: sdmmc3_mx-0 {
  90. pins1 {
  91. pinmux = <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
  92. <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
  93. <STM32_PINMUX('F', 1, AF9)>, /* SDMMC3_CMD */
  94. <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
  95. <STM32_PINMUX('F', 5, AF9)>; /* SDMMC3_D2 */
  96. bias-disable;
  97. drive-push-pull;
  98. slew-rate = <1>;
  99. };
  100. pins2 {
  101. pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
  102. bias-disable;
  103. drive-push-pull;
  104. slew-rate = <2>;
  105. };
  106. };
  107. uart4_pins_mx: uart4_mx-0 {
  108. pins1 {
  109. pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
  110. bias-disable;
  111. };
  112. pins2 {
  113. pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
  114. bias-disable;
  115. drive-push-pull;
  116. slew-rate = <0>;
  117. };
  118. };
  119. };
  120. &pinctrl_z {
  121. i2c4_pins_z_mx: i2c4_mx-0 {
  122. pins {
  123. pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
  124. <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
  125. bias-disable;
  126. drive-open-drain;
  127. slew-rate = <0>;
  128. };
  129. };
  130. };
  131. &rcc {
  132. st,csi-cal;
  133. st,hsi-cal;
  134. st,cal-sec = <60>;
  135. st,clksrc = <
  136. CLK_MPU_PLL1P
  137. CLK_AXI_PLL2P
  138. CLK_MCU_PLL3P
  139. CLK_PLL12_HSE
  140. CLK_PLL3_HSE
  141. CLK_PLL4_HSE
  142. CLK_RTC_LSE
  143. CLK_MCO1_DISABLED
  144. CLK_MCO2_DISABLED
  145. >;
  146. st,clkdiv = <
  147. 1 /*MPU*/
  148. 0 /*AXI*/
  149. 0 /*MCU*/
  150. 1 /*APB1*/
  151. 1 /*APB2*/
  152. 1 /*APB3*/
  153. 1 /*APB4*/
  154. 2 /*APB5*/
  155. 23 /*RTC*/
  156. 0 /*MCO1*/
  157. 0 /*MCO2*/
  158. >;
  159. st,pkcs = <
  160. CLK_CKPER_HSE
  161. CLK_ETH_PLL3Q
  162. CLK_SDMMC12_PLL4P
  163. CLK_DSI_DSIPLL
  164. CLK_STGEN_HSE
  165. CLK_USBPHY_HSE
  166. CLK_SPI2S1_DISABLED
  167. CLK_SPI2S23_PLL3Q
  168. CLK_SPI45_PCLK2
  169. CLK_SPI6_DISABLED
  170. CLK_I2C46_HSI
  171. CLK_SDMMC3_PLL4P
  172. CLK_USBO_USBPHY
  173. CLK_ADC_CKPER
  174. CLK_CEC_DISABLED
  175. CLK_I2C12_HSI
  176. CLK_I2C35_PCLK1
  177. CLK_UART1_DISABLED
  178. CLK_UART24_HSI
  179. CLK_UART35_HSI
  180. CLK_UART6_DISABLED
  181. CLK_UART78_DISABLED
  182. CLK_SPDIF_DISABLED
  183. CLK_SAI1_DISABLED
  184. CLK_SAI2_CKPER
  185. CLK_SAI3_DISABLED
  186. CLK_SAI4_DISABLED
  187. CLK_RNG1_LSI
  188. CLK_LPTIM1_DISABLED
  189. CLK_LPTIM23_DISABLED
  190. CLK_LPTIM45_DISABLED
  191. >;
  192. pll1:st,pll@0 {
  193. cfg = < 2 80 0 1 1 PQR(1,0,0) >;
  194. frac = < 0x800>;
  195. };
  196. pll2:st,pll@1 {
  197. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  198. frac = < 0x1400>;
  199. };
  200. pll3:st,pll@2 {
  201. cfg = < 1 61 3 5 36 PQR(1,1,0) >;
  202. frac = < 0x1000 >;
  203. };
  204. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  205. pll4: st,pll@3 {
  206. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  207. };
  208. };
  209. &bsec{
  210. status = "okay";
  211. secure-status = "okay";
  212. board_id: board_id@ec {
  213. reg = <0xec 0x4>;
  214. status = "okay";
  215. secure-status = "okay";
  216. };
  217. };
  218. &etzpc{
  219. st,decprot = <
  220. /*"Non Secured" peripherals*/
  221. DECPROT(STM32MP1_ETZPC_DCMI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  222. DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  223. DECPROT(STM32MP1_ETZPC_I2C1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  224. DECPROT(STM32MP1_ETZPC_I2C2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  225. DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  226. DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  227. DECPROT(STM32MP1_ETZPC_SPI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  228. DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  229. DECPROT(STM32MP1_ETZPC_SAI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  230. DECPROT(STM32MP1_ETZPC_SDMMC3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  231. DECPROT(STM32MP1_ETZPC_DLYBSD3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  232. DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  233. DECPROT(STM32MP1_ETZPC_TIM5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  234. DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  235. DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  236. /*Restriction: following IDs are not managed - please to use User-Section if needed:
  237. STM32MP1_ETZPC_DMA1_ID, STM32MP1_ETZPC_DMA2_ID, STM32MP1_ETZPC_DMAMUX_ID,
  238. STM32MP1_ETZPC_SRAMx_ID, STM32MP1_ETZPC_RETRAM_ID, STM32MP1_ETZPC_BKPSRAM_ID*/
  239. /*STM32CubeMX generates a basic and standard configuration for ETZPC.
  240. Additional device configurations can be added here if needed.
  241. "etzpc" node could be also overloaded in "addons" User-Section.*/
  242. >;
  243. secure-status = "okay";
  244. };
  245. &i2c4{
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&i2c4_pins_z_mx>;
  248. status = "okay";
  249. secure-status = "okay";
  250. i2c-scl-rising-time-ns = <185>;
  251. i2c-scl-falling-time-ns = <20>;
  252. pmic: stpmic@33 {
  253. compatible = "st,stpmic1";
  254. reg = <0x33>;
  255. interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
  256. interrupt-controller;
  257. #interrupt-cells = <2>;
  258. status = "okay";
  259. st,main-control-register = <0x04>;
  260. st,vin-control-register = <0xc0>;
  261. st,usb-control-register = <0x20>;
  262. regulators {
  263. compatible = "st,stpmic1-regulators";
  264. ldo1-supply = <&v3v3>;
  265. ldo3-supply = <&vdd_ddr>;
  266. ldo6-supply = <&v3v3>;
  267. vddcore: buck1 {
  268. regulator-name = "vddcore";
  269. regulator-min-microvolt = <1200000>;
  270. regulator-max-microvolt = <1350000>;
  271. regulator-always-on;
  272. regulator-initial-mode = <0>;
  273. regulator-over-current-protection;
  274. lp-stop {
  275. regulator-on-in-suspend;
  276. regulator-suspend-microvolt = <1200000>;
  277. };
  278. standby-ddr-sr {
  279. regulator-off-in-suspend;
  280. };
  281. standby-ddr-off {
  282. regulator-off-in-suspend;
  283. };
  284. };
  285. vdd_ddr: buck2 {
  286. regulator-name = "vdd_ddr";
  287. regulator-min-microvolt = <1350000>;
  288. regulator-max-microvolt = <1350000>;
  289. regulator-always-on;
  290. regulator-initial-mode = <0>;
  291. regulator-over-current-protection;
  292. lp-stop {
  293. regulator-suspend-microvolt = <1350000>;
  294. regulator-on-in-suspend;
  295. };
  296. standby-ddr-sr {
  297. regulator-suspend-microvolt = <1350000>;
  298. regulator-on-in-suspend;
  299. };
  300. standby-ddr-off {
  301. regulator-off-in-suspend;
  302. };
  303. };
  304. vdd: buck3 {
  305. regulator-name = "vdd";
  306. regulator-min-microvolt = <3300000>;
  307. regulator-max-microvolt = <3300000>;
  308. regulator-always-on;
  309. st,mask-reset;
  310. regulator-initial-mode = <0>;
  311. regulator-over-current-protection;
  312. lp-stop {
  313. regulator-suspend-microvolt = <3300000>;
  314. regulator-on-in-suspend;
  315. };
  316. standby-ddr-sr {
  317. regulator-suspend-microvolt = <3300000>;
  318. regulator-on-in-suspend;
  319. };
  320. standby-ddr-off {
  321. regulator-suspend-microvolt = <3300000>;
  322. regulator-on-in-suspend;
  323. };
  324. };
  325. v3v3: buck4 {
  326. regulator-name = "v3v3";
  327. regulator-min-microvolt = <3300000>;
  328. regulator-max-microvolt = <3300000>;
  329. regulator-always-on;
  330. regulator-over-current-protection;
  331. regulator-initial-mode = <0>;
  332. lp-stop {
  333. regulator-suspend-microvolt = <3300000>;
  334. regulator-on-in-suspend;
  335. };
  336. standby-ddr-sr {
  337. regulator-off-in-suspend;
  338. };
  339. standby-ddr-off {
  340. regulator-off-in-suspend;
  341. };
  342. };
  343. v1v8_audio: ldo1 {
  344. regulator-name = "v1v8_audio";
  345. regulator-min-microvolt = <1800000>;
  346. regulator-max-microvolt = <1800000>;
  347. regulator-always-on;
  348. standby-ddr-sr {
  349. regulator-off-in-suspend;
  350. };
  351. standby-ddr-off {
  352. regulator-off-in-suspend;
  353. };
  354. };
  355. v3v3_hdmi: ldo2 {
  356. regulator-name = "v3v3_hdmi";
  357. regulator-min-microvolt = <3300000>;
  358. regulator-max-microvolt = <3300000>;
  359. regulator-always-on;
  360. standby-ddr-sr {
  361. regulator-off-in-suspend;
  362. };
  363. standby-ddr-off {
  364. regulator-off-in-suspend;
  365. };
  366. };
  367. vtt_ddr: ldo3 {
  368. regulator-name = "vtt_ddr";
  369. regulator-min-microvolt = <500000>;
  370. regulator-max-microvolt = <750000>;
  371. regulator-always-on;
  372. regulator-over-current-protection;
  373. lp-stop {
  374. regulator-off-in-suspend;
  375. };
  376. standby-ddr-sr {
  377. regulator-off-in-suspend;
  378. };
  379. standby-ddr-off {
  380. regulator-off-in-suspend;
  381. };
  382. };
  383. vdd_usb: ldo4 {
  384. regulator-name = "vdd_usb";
  385. regulator-min-microvolt = <3300000>;
  386. regulator-max-microvolt = <3300000>;
  387. standby-ddr-sr {
  388. regulator-off-in-suspend;
  389. };
  390. standby-ddr-off {
  391. regulator-off-in-suspend;
  392. };
  393. };
  394. vdda: ldo5 {
  395. regulator-name = "vdda";
  396. regulator-min-microvolt = <2900000>;
  397. regulator-max-microvolt = <2900000>;
  398. regulator-boot-on;
  399. standby-ddr-sr {
  400. regulator-off-in-suspend;
  401. };
  402. standby-ddr-off {
  403. regulator-off-in-suspend;
  404. };
  405. };
  406. v1v2_hdmi: ldo6 {
  407. regulator-name = "v1v2_hdmi";
  408. regulator-min-microvolt = <1200000>;
  409. regulator-max-microvolt = <1200000>;
  410. regulator-always-on;
  411. standby-ddr-sr {
  412. regulator-off-in-suspend;
  413. };
  414. standby-ddr-off {
  415. regulator-off-in-suspend;
  416. };
  417. };
  418. vref_ddr: vref_ddr {
  419. regulator-name = "vref_ddr";
  420. regulator-always-on;
  421. regulator-over-current-protection;
  422. lp-stop {
  423. regulator-on-in-suspend;
  424. };
  425. standby-ddr-sr {
  426. regulator-on-in-suspend;
  427. };
  428. standby-ddr-off {
  429. regulator-off-in-suspend;
  430. };
  431. };
  432. };
  433. };
  434. };
  435. &iwdg2{
  436. status = "okay";
  437. secure-status = "okay";
  438. timeout-sec = <32>;
  439. };
  440. &pwr{
  441. status = "okay";
  442. secure-status = "okay";
  443. system_suspend_supported_soc_modes = <
  444. STM32_PM_CSLEEP_RUN
  445. STM32_PM_CSTOP_ALLOW_LP_STOP
  446. STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR
  447. >;
  448. system_off_soc_mode = <STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF>;
  449. pwr-regulators {
  450. vdd-supply = <&vdd>;
  451. };
  452. };
  453. &rcc{
  454. status = "okay";
  455. secure-status = "okay";
  456. };
  457. &rng1{
  458. status = "okay";
  459. secure-status = "okay";
  460. };
  461. &rtc{
  462. status = "okay";
  463. secure-status = "okay";
  464. };
  465. &sdmmc1{
  466. pinctrl-names = "default";
  467. pinctrl-0 = <&sdmmc1_pins_mx>;
  468. status = "okay";
  469. broken-cd;
  470. st,neg-edge;
  471. bus-width = <4>;
  472. vmmc-supply = <&v3v3>;
  473. };
  474. &sdmmc2{
  475. pinctrl-names = "default";
  476. pinctrl-0 = <&sdmmc2_pins_mx>;
  477. status = "okay";
  478. };
  479. &sdmmc3{
  480. pinctrl-names = "default";
  481. pinctrl-0 = <&sdmmc3_pins_mx>;
  482. status = "okay";
  483. };
  484. &tamp{
  485. status = "okay";
  486. secure-status = "okay";
  487. };
  488. &uart4{
  489. pinctrl-names = "default";
  490. pinctrl-0 = <&uart4_pins_mx>;
  491. status = "okay";
  492. };
  493. /delete-node/ &qspi_bk1_pins_a;
  494. /delete-node/ &qspi_bk2_pins_a;
  495. /delete-node/ &qspi_clk_pins_a;
  496. /delete-node/ &sdmmc1_b4_pins_a;
  497. /delete-node/ &sdmmc1_dir_pins_a;
  498. /delete-node/ &sdmmc1_dir_pins_b;
  499. /delete-node/ &sdmmc2_b4_pins_a;
  500. /delete-node/ &sdmmc2_d47_pins_a;
  501. /delete-node/ &uart4_pins_a;
  502. /delete-node/ &uart7_pins_a;
  503. /delete-node/ &usart3_pins_a;
  504. /delete-node/ &usart3_pins_b;
  505. /delete-node/ &i2c4_pins_a;