402-mips-pr17770.patch 406 B

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  1. --- gcc-3.4.2/gcc/config/mips/mips.md 2004-06-25 02:35:30.000000000 -0500
  2. +++ gcc-3.4-cvs/gcc/config/mips/mips.md 2004-10-26 01:54:56.000000000 -0500
  3. @@ -4073,8 +4073,7 @@
  4. "!TARGET_MIPS16"
  5. "lwl\t%0,%2"
  6. [(set_attr "type" "load")
  7. - (set_attr "mode" "SI")
  8. - (set_attr "hazard" "none")])
  9. + (set_attr "mode" "SI")])
  10. (define_insn "mov_lwr"
  11. [(set (match_operand:SI 0 "register_operand" "=d")