Config.in 11 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. config BR2_ARCH_HAS_FDPIC_SUPPORT
  13. bool
  14. choice
  15. prompt "Target Architecture"
  16. default BR2_i386
  17. help
  18. Select the target architecture family to build for.
  19. config BR2_arcle
  20. bool "ARC (little endian)"
  21. select BR2_ARCH_HAS_MMU_MANDATORY
  22. help
  23. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  24. that can be used from deeply embedded to high performance host
  25. applications. Little endian.
  26. config BR2_arceb
  27. bool "ARC (big endian)"
  28. select BR2_ARCH_HAS_MMU_MANDATORY
  29. help
  30. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  31. that can be used from deeply embedded to high performance host
  32. applications. Big endian.
  33. config BR2_arm
  34. bool "ARM (little endian)"
  35. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  36. help
  37. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  38. set architecture (ISA) developed by ARM Holdings. Little endian.
  39. http://www.arm.com/
  40. http://en.wikipedia.org/wiki/ARM
  41. config BR2_armeb
  42. bool "ARM (big endian)"
  43. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  44. help
  45. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  46. set architecture (ISA) developed by ARM Holdings. Big endian.
  47. http://www.arm.com/
  48. http://en.wikipedia.org/wiki/ARM
  49. config BR2_aarch64
  50. bool "AArch64 (little endian)"
  51. select BR2_ARCH_IS_64
  52. select BR2_ARCH_HAS_MMU_MANDATORY
  53. help
  54. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  55. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  56. http://en.wikipedia.org/wiki/ARM
  57. config BR2_aarch64_be
  58. bool "AArch64 (big endian)"
  59. select BR2_ARCH_IS_64
  60. select BR2_ARCH_HAS_MMU_MANDATORY
  61. help
  62. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  63. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  64. http://en.wikipedia.org/wiki/ARM
  65. config BR2_bfin
  66. bool "Blackfin"
  67. select BR2_ARCH_HAS_FDPIC_SUPPORT
  68. help
  69. The Blackfin is a family of 16 or 32-bit microprocessors developed,
  70. manufactured and marketed by Analog Devices.
  71. http://www.analog.com/
  72. http://en.wikipedia.org/wiki/Blackfin
  73. config BR2_i386
  74. bool "i386"
  75. select BR2_ARCH_HAS_MMU_MANDATORY
  76. help
  77. Intel i386 architecture compatible microprocessor
  78. http://en.wikipedia.org/wiki/I386
  79. config BR2_m68k
  80. bool "m68k"
  81. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  82. help
  83. Motorola 68000 family microprocessor
  84. http://en.wikipedia.org/wiki/M68k
  85. config BR2_microblazeel
  86. bool "Microblaze AXI (little endian)"
  87. select BR2_ARCH_HAS_MMU_MANDATORY
  88. help
  89. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
  90. based architecture (little endian)
  91. http://www.xilinx.com
  92. http://en.wikipedia.org/wiki/Microblaze
  93. config BR2_microblazebe
  94. bool "Microblaze non-AXI (big endian)"
  95. select BR2_ARCH_HAS_MMU_MANDATORY
  96. help
  97. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
  98. based architecture (non-AXI, big endian)
  99. http://www.xilinx.com
  100. http://en.wikipedia.org/wiki/Microblaze
  101. config BR2_mips
  102. bool "MIPS (big endian)"
  103. select BR2_ARCH_HAS_MMU_MANDATORY
  104. help
  105. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  106. http://www.mips.com/
  107. http://en.wikipedia.org/wiki/MIPS_Technologies
  108. config BR2_mipsel
  109. bool "MIPS (little endian)"
  110. select BR2_ARCH_HAS_MMU_MANDATORY
  111. help
  112. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  113. http://www.mips.com/
  114. http://en.wikipedia.org/wiki/MIPS_Technologies
  115. config BR2_mips64
  116. bool "MIPS64 (big endian)"
  117. select BR2_ARCH_IS_64
  118. select BR2_ARCH_HAS_MMU_MANDATORY
  119. help
  120. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  121. http://www.mips.com/
  122. http://en.wikipedia.org/wiki/MIPS_Technologies
  123. config BR2_mips64el
  124. bool "MIPS64 (little endian)"
  125. select BR2_ARCH_IS_64
  126. select BR2_ARCH_HAS_MMU_MANDATORY
  127. help
  128. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  129. http://www.mips.com/
  130. http://en.wikipedia.org/wiki/MIPS_Technologies
  131. config BR2_nios2
  132. bool "Nios II"
  133. select BR2_ARCH_HAS_MMU_MANDATORY
  134. help
  135. Nios II is a soft core processor from Altera Corporation.
  136. http://www.altera.com/
  137. http://en.wikipedia.org/wiki/Nios_II
  138. config BR2_or1k
  139. bool "OpenRISC"
  140. select BR2_ARCH_HAS_MMU_MANDATORY
  141. help
  142. OpenRISC is a free and open processor for embedded system.
  143. http://openrisc.io
  144. config BR2_powerpc
  145. bool "PowerPC"
  146. select BR2_ARCH_HAS_MMU_MANDATORY
  147. help
  148. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  149. Big endian.
  150. http://www.power.org/
  151. http://en.wikipedia.org/wiki/Powerpc
  152. config BR2_powerpc64
  153. bool "PowerPC64 (big endian)"
  154. select BR2_ARCH_IS_64
  155. select BR2_ARCH_HAS_MMU_MANDATORY
  156. help
  157. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  158. Big endian.
  159. http://www.power.org/
  160. http://en.wikipedia.org/wiki/Powerpc
  161. config BR2_powerpc64le
  162. bool "PowerPC64 (little endian)"
  163. select BR2_ARCH_IS_64
  164. select BR2_ARCH_HAS_MMU_MANDATORY
  165. help
  166. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  167. Little endian.
  168. http://www.power.org/
  169. http://en.wikipedia.org/wiki/Powerpc
  170. config BR2_sh
  171. bool "SuperH"
  172. select BR2_ARCH_HAS_MMU_OPTIONAL
  173. help
  174. SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
  175. instruction set architecture (ISA) developed by Hitachi.
  176. http://www.hitachi.com/
  177. http://en.wikipedia.org/wiki/SuperH
  178. config BR2_sparc
  179. bool "SPARC"
  180. select BR2_ARCH_HAS_MMU_MANDATORY
  181. help
  182. SPARC (from Scalable Processor Architecture) is a RISC instruction
  183. set architecture (ISA) developed by Sun Microsystems.
  184. http://www.oracle.com/sun
  185. http://en.wikipedia.org/wiki/Sparc
  186. config BR2_sparc64
  187. bool "SPARC64"
  188. select BR2_ARCH_IS_64
  189. select BR2_ARCH_HAS_MMU_MANDATORY
  190. help
  191. SPARC (from Scalable Processor Architecture) is a RISC instruction
  192. set architecture (ISA) developed by Sun Microsystems.
  193. http://www.oracle.com/sun
  194. http://en.wikipedia.org/wiki/Sparc
  195. config BR2_x86_64
  196. bool "x86_64"
  197. select BR2_ARCH_IS_64
  198. select BR2_ARCH_HAS_MMU_MANDATORY
  199. help
  200. x86-64 is an extension of the x86 instruction set (Intel i386
  201. architecture compatible microprocessor).
  202. http://en.wikipedia.org/wiki/X86_64
  203. config BR2_xtensa
  204. bool "Xtensa"
  205. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  206. help
  207. Xtensa is a Tensilica processor IP architecture.
  208. http://en.wikipedia.org/wiki/Xtensa
  209. http://www.tensilica.com/
  210. endchoice
  211. # The following string values are defined by the individual
  212. # Config.in.$ARCH files
  213. config BR2_ARCH
  214. string
  215. config BR2_ENDIAN
  216. string
  217. config BR2_GCC_TARGET_ARCH
  218. string
  219. config BR2_GCC_TARGET_ABI
  220. string
  221. config BR2_GCC_TARGET_CPU
  222. string
  223. config BR2_GCC_TARGET_CPU_REVISION
  224. string
  225. # The value of this option will be passed as --with-fpu=<value> when
  226. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  227. # wrapper (external toolchain)
  228. config BR2_GCC_TARGET_FPU
  229. string
  230. # The value of this option will be passed as --with-float=<value> when
  231. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  232. # wrapper (external toolchain)
  233. config BR2_GCC_TARGET_FLOAT_ABI
  234. string
  235. # The value of this option will be passed as --with-mode=<value> when
  236. # building gcc (internal backend) or -m<value> in the toolchain
  237. # wrapper (external toolchain)
  238. config BR2_GCC_TARGET_MODE
  239. string
  240. # Must be selected by binary formats that support shared libraries.
  241. config BR2_BINFMT_SUPPORTS_SHARED
  242. bool
  243. # Set up target binary format
  244. choice
  245. prompt "Target Binary Format"
  246. default BR2_BINFMT_ELF if BR2_USE_MMU
  247. default BR2_BINFMT_FDPIC if BR2_ARCH_HAS_FDPIC_SUPPORT
  248. default BR2_BINFMT_FLAT
  249. config BR2_BINFMT_ELF
  250. bool "ELF"
  251. depends on BR2_USE_MMU
  252. select BR2_BINFMT_SUPPORTS_SHARED
  253. help
  254. ELF (Executable and Linkable Format) is a format for libraries and
  255. executables used across different architectures and operating
  256. systems.
  257. config BR2_BINFMT_FDPIC
  258. bool "FDPIC"
  259. depends on BR2_ARCH_HAS_FDPIC_SUPPORT
  260. select BR2_BINFMT_SUPPORTS_SHARED
  261. help
  262. ELF FDPIC binaries are based on ELF, but allow the individual load
  263. segments of a binary to be located in memory independently of each
  264. other. This makes this format ideal for use in environments where no
  265. MMU is available.
  266. config BR2_BINFMT_FLAT
  267. bool "FLAT"
  268. depends on !BR2_USE_MMU
  269. help
  270. FLAT binary is a relatively simple and lightweight executable format
  271. based on the original a.out format. It is widely used in environment
  272. where no MMU is available.
  273. endchoice
  274. # Set up flat binary type
  275. choice
  276. prompt "FLAT Binary type"
  277. depends on BR2_BINFMT_FLAT
  278. default BR2_BINFMT_FLAT_ONE
  279. config BR2_BINFMT_FLAT_ONE
  280. bool "One memory region"
  281. help
  282. All segments are linked into one memory region.
  283. config BR2_BINFMT_FLAT_SEP_DATA
  284. bool "Separate data and code region"
  285. # this FLAT binary type technically exists on m68k, but fails
  286. # to build numerous packages: due to architecture limitation,
  287. # big functions cannot be built in this mode. They cause build
  288. # failures such as "Tried to convert PC relative branch to
  289. # absolute jump" or "error: value -yyyyy out of range".
  290. depends on BR2_bfin
  291. help
  292. Allow for the data and text segments to be separated and placed in
  293. different regions of memory.
  294. config BR2_BINFMT_FLAT_SHARED
  295. bool "Shared binary"
  296. depends on BR2_m68k || BR2_bfin
  297. # Even though this really generates shared binaries, there is no libdl
  298. # and dlopen() cannot be used. So packages that require shared
  299. # libraries cannot be built. Therefore, we don't select
  300. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  301. # Although this adds -static to the compilation, that's not a problem
  302. # because the -mid-shared-library option overrides it.
  303. help
  304. Allow to load and link indiviual FLAT binaries at run time.
  305. endchoice
  306. if BR2_arcle || BR2_arceb
  307. source "arch/Config.in.arc"
  308. endif
  309. if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
  310. source "arch/Config.in.arm"
  311. endif
  312. if BR2_bfin
  313. source "arch/Config.in.bfin"
  314. endif
  315. if BR2_m68k
  316. source "arch/Config.in.m68k"
  317. endif
  318. if BR2_microblazeel || BR2_microblazebe
  319. source "arch/Config.in.microblaze"
  320. endif
  321. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  322. source "arch/Config.in.mips"
  323. endif
  324. if BR2_nios2
  325. source "arch/Config.in.nios2"
  326. endif
  327. if BR2_or1k
  328. source "arch/Config.in.or1k"
  329. endif
  330. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  331. source "arch/Config.in.powerpc"
  332. endif
  333. if BR2_sh
  334. source "arch/Config.in.sh"
  335. endif
  336. if BR2_sparc || BR2_sparc64
  337. source "arch/Config.in.sparc"
  338. endif
  339. if BR2_i386 || BR2_x86_64
  340. source "arch/Config.in.x86"
  341. endif
  342. if BR2_xtensa
  343. source "arch/Config.in.xtensa"
  344. endif
  345. endmenu # Target options