2
1

Config.in 8.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370
  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. choice
  9. prompt "Target Architecture"
  10. default BR2_i386
  11. help
  12. Select the target architecture family to build for.
  13. config BR2_arcle
  14. bool "ARC (little endian)"
  15. help
  16. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  17. that can be used from deeply embedded to high performance host
  18. applications. Little endian.
  19. config BR2_arceb
  20. bool "ARC (big endian)"
  21. help
  22. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  23. that can be used from deeply embedded to high performance host
  24. applications. Big endian.
  25. config BR2_arm
  26. bool "ARM (little endian)"
  27. help
  28. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  29. set architecture (ISA) developed by ARM Holdings. Little endian.
  30. http://www.arm.com/
  31. http://en.wikipedia.org/wiki/ARM
  32. config BR2_armeb
  33. bool "ARM (big endian)"
  34. help
  35. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  36. set architecture (ISA) developed by ARM Holdings. Big endian.
  37. http://www.arm.com/
  38. http://en.wikipedia.org/wiki/ARM
  39. config BR2_aarch64
  40. bool "AArch64"
  41. select BR2_ARCH_IS_64
  42. help
  43. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  44. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  45. http://en.wikipedia.org/wiki/ARM
  46. config BR2_avr32
  47. bool "AVR32"
  48. select BR2_SOFT_FLOAT
  49. # This architecture is obsolete and complicated to maintain to
  50. # do the lack of upstream support in the major toolchain
  51. # components. If you're interested by AVR32, contact the
  52. # Buildroot community. Otherwise, its support will be removed
  53. # by the 2015.02 release.
  54. depends on BR2_DEPRECATED_SINCE_2014_08
  55. help
  56. The AVR32 is a 32-bit RISC microprocessor architecture designed by
  57. Atmel.
  58. http://www.atmel.com/
  59. http://en.wikipedia.org/wiki/Avr32
  60. config BR2_bfin
  61. bool "Blackfin"
  62. help
  63. The Blackfin is a family of 16 or 32-bit microprocessors developed,
  64. manufactured and marketed by Analog Devices.
  65. http://www.analog.com/
  66. http://en.wikipedia.org/wiki/Blackfin
  67. config BR2_i386
  68. bool "i386"
  69. help
  70. Intel i386 architecture compatible microprocessor
  71. http://en.wikipedia.org/wiki/I386
  72. config BR2_m68k
  73. bool "m68k"
  74. depends on BROKEN # ice in uclibc / inet_ntoa_r
  75. help
  76. Motorola 68000 family microprocessor
  77. http://en.wikipedia.org/wiki/M68k
  78. config BR2_microblazeel
  79. bool "Microblaze AXI (little endian)"
  80. help
  81. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
  82. based architecture (little endian)
  83. http://www.xilinx.com
  84. http://en.wikipedia.org/wiki/Microblaze
  85. config BR2_microblazebe
  86. bool "Microblaze non-AXI (big endian)"
  87. help
  88. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
  89. based architecture (non-AXI, big endian)
  90. http://www.xilinx.com
  91. http://en.wikipedia.org/wiki/Microblaze
  92. config BR2_mips
  93. bool "MIPS (big endian)"
  94. help
  95. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  96. http://www.mips.com/
  97. http://en.wikipedia.org/wiki/MIPS_Technologies
  98. config BR2_mipsel
  99. bool "MIPS (little endian)"
  100. help
  101. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  102. http://www.mips.com/
  103. http://en.wikipedia.org/wiki/MIPS_Technologies
  104. config BR2_mips64
  105. bool "MIPS64 (big endian)"
  106. select BR2_ARCH_IS_64
  107. help
  108. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  109. http://www.mips.com/
  110. http://en.wikipedia.org/wiki/MIPS_Technologies
  111. config BR2_mips64el
  112. bool "MIPS64 (little endian)"
  113. select BR2_ARCH_IS_64
  114. help
  115. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  116. http://www.mips.com/
  117. http://en.wikipedia.org/wiki/MIPS_Technologies
  118. config BR2_nios2
  119. bool "Nios II"
  120. help
  121. Nios II is a soft core processor from Altera Corporation.
  122. http://www.altera.com/
  123. http://en.wikipedia.org/wiki/Nios_II
  124. config BR2_powerpc
  125. bool "PowerPC"
  126. help
  127. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  128. Big endian.
  129. http://www.power.org/
  130. http://en.wikipedia.org/wiki/Powerpc
  131. config BR2_powerpc64
  132. bool "PowerPC64 (big endian)"
  133. select BR2_ARCH_IS_64
  134. help
  135. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  136. Big endian.
  137. http://www.power.org/
  138. http://en.wikipedia.org/wiki/Powerpc
  139. config BR2_powerpc64le
  140. bool "PowerPC64 (little endian)"
  141. select BR2_ARCH_IS_64
  142. help
  143. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  144. Little endian.
  145. http://www.power.org/
  146. http://en.wikipedia.org/wiki/Powerpc
  147. config BR2_sh
  148. bool "SuperH"
  149. help
  150. SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
  151. instruction set architecture (ISA) developed by Hitachi.
  152. http://www.hitachi.com/
  153. http://en.wikipedia.org/wiki/SuperH
  154. config BR2_sh64
  155. bool "SuperH64"
  156. help
  157. SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
  158. instruction set architecture (ISA) developed by Hitachi.
  159. http://www.hitachi.com/
  160. http://en.wikipedia.org/wiki/SuperH
  161. config BR2_sparc
  162. bool "SPARC"
  163. help
  164. SPARC (from Scalable Processor Architecture) is a RISC instruction
  165. set architecture (ISA) developed by Sun Microsystems.
  166. http://www.oracle.com/sun
  167. http://en.wikipedia.org/wiki/Sparc
  168. config BR2_x86_64
  169. bool "x86_64"
  170. select BR2_ARCH_IS_64
  171. help
  172. x86-64 is an extension of the x86 instruction set (Intel i386
  173. architecture compatible microprocessor).
  174. http://en.wikipedia.org/wiki/X86_64
  175. config BR2_xtensa
  176. bool "Xtensa"
  177. help
  178. Xtensa is a Tensilica processor IP architecture.
  179. http://en.wikipedia.org/wiki/Xtensa
  180. http://www.tensilica.com/
  181. endchoice
  182. # The following string values are defined by the individual
  183. # Config.in.$ARCH files
  184. config BR2_ARCH
  185. string
  186. config BR2_ENDIAN
  187. string
  188. config BR2_GCC_TARGET_ARCH
  189. string
  190. config BR2_GCC_TARGET_ABI
  191. string
  192. config BR2_GCC_TARGET_CPU
  193. string
  194. config BR2_GCC_TARGET_CPU_REVISION
  195. string
  196. # The value of this option will be passed as --with-fpu=<value> when
  197. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  198. # wrapper (external toolchain)
  199. config BR2_GCC_TARGET_FPU
  200. string
  201. # The value of this option will be passed as --with-float=<value> when
  202. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  203. # wrapper (external toolchain)
  204. config BR2_GCC_TARGET_FLOAT_ABI
  205. string
  206. # The value of this option will be passed as --with-mode=<value> when
  207. # building gcc (internal backend) or -m<value> in the toolchain
  208. # wrapper (external toolchain)
  209. config BR2_GCC_TARGET_MODE
  210. string
  211. # If the architecture has atomic operations, select this:
  212. config BR2_ARCH_HAS_ATOMICS
  213. bool
  214. # Set up target binary format
  215. choice
  216. prompt "Target Binary Format"
  217. depends on BR2_bfin || BR2_m68k
  218. default BR2_BINFMT_FDPIC
  219. config BR2_BINFMT_ELF
  220. bool "ELF"
  221. depends on !BR2_bfin && !BR2_m68k
  222. help
  223. ELF (Executable and Linkable Format) is a format for libraries and
  224. executables used across different architectures and operating
  225. systems.
  226. config BR2_BINFMT_FDPIC
  227. bool "FDPIC"
  228. depends on BR2_bfin || BR2_m68k
  229. help
  230. ELF FDPIC binaries are based on ELF, but allow the individual load
  231. segments of a binary to be located in memory independently of each
  232. other. This makes this format ideal for use in environments where no
  233. MMU is available.
  234. config BR2_BINFMT_FLAT
  235. bool "FLAT"
  236. depends on BR2_bfin || BR2_m68k
  237. select BR2_PREFER_STATIC_LIB
  238. help
  239. FLAT binary is a relatively simple and lightweight executable format
  240. based on the original a.out format. It is widely used in environment
  241. where no MMU is available.
  242. endchoice
  243. # Set up flat binary type
  244. choice
  245. prompt "FLAT Binary type"
  246. depends on BR2_BINFMT_FLAT
  247. default BR2_BINFMT_FLAT_ONE
  248. config BR2_BINFMT_FLAT_ONE
  249. bool "One memory region"
  250. help
  251. All segments are linked into one memory region.
  252. config BR2_BINFMT_FLAT_SEP_DATA
  253. bool "Separate data and code region"
  254. depends on BR2_bfin || BR2_m68k
  255. help
  256. Allow for the data and text segments to be separated and placed in
  257. different regions of memory.
  258. config BR2_BINFMT_FLAT_SHARED
  259. bool "Shared binary"
  260. depends on BR2_bfin || BR2_m68k
  261. help
  262. Allow to load and link indiviual FLAT binaries at run time.
  263. endchoice
  264. if BR2_arcle || BR2_arceb
  265. source "arch/Config.in.arc"
  266. endif
  267. if BR2_arm || BR2_armeb
  268. source "arch/Config.in.arm"
  269. endif
  270. if BR2_aarch64
  271. source "arch/Config.in.aarch64"
  272. endif
  273. if BR2_avr32
  274. source "arch/Config.in.avr32"
  275. endif
  276. if BR2_bfin
  277. source "arch/Config.in.bfin"
  278. endif
  279. if BR2_m68k
  280. source "arch/Config.in.m68k"
  281. endif
  282. if BR2_microblazeel || BR2_microblazebe
  283. source "arch/Config.in.microblaze"
  284. endif
  285. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  286. source "arch/Config.in.mips"
  287. endif
  288. if BR2_nios2
  289. source "arch/Config.in.nios2"
  290. endif
  291. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  292. source "arch/Config.in.powerpc"
  293. endif
  294. if BR2_sh || BR2_sh64
  295. source "arch/Config.in.sh"
  296. endif
  297. if BR2_sparc
  298. source "arch/Config.in.sparc"
  299. endif
  300. if BR2_i386 || BR2_x86_64
  301. source "arch/Config.in.x86"
  302. endif
  303. if BR2_xtensa
  304. source "arch/Config.in.xtensa"
  305. endif
  306. endmenu # Target options