/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ /* * Copyright (C) STMicroelectronics 2020 - All Rights Reserved * Author: STM32CubeMX code generation for STMicroelectronics. */ /* For more information on Device Tree configuration, please refer to * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration */ /dts-v1/; #include #include #include #include #include "osd32mp1_ddr.dtsi" #include "stm32mp157.dtsi" #include "stm32mp15xc.dtsi" #include "stm32mp15xxac-pinctrl.dtsi" #include "stm32mp15-ddr.dtsi" / { model = "Octavo OSD32MP1 BRK board"; compatible = "st,stm32mp157c-osd32mp1-brk", "st,stm32mp157"; memory@c0000000{ device_type = "memory"; reg = <0xc0000000 0x20000000>; }; vin:vin{ compatible = "regulator-fixed"; regulator-name = "vin"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; }; aliases{ serial0 = &uart4; }; chosen{ stdout-path = "serial0:115200n8"; }; clocks { clk_lse: clk-lse { st,drive = < LSEDRV_MEDIUM_HIGH >; }; }; }; &clk_hse { st,digbypass; }; &pinctrl { sdmmc1_pins_mx: sdmmc1_mx-0 { pins1 { pinmux = , /* SDMMC1_D0 */ , /* SDMMC1_D1 */ , /* SDMMC1_D2 */ , /* SDMMC1_D3 */ ; /* SDMMC1_CMD */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* SDMMC1_CK */ bias-disable; drive-push-pull; slew-rate = <2>; }; }; uart4_pins_mx: uart4_mx-0 { pins1 { pinmux = ; /* UART4_RX */ bias-disable; }; pins2 { pinmux = ; /* UART4_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; }; /* USER CODE BEGIN pinctrl */ /* USER CODE END pinctrl */ }; &pinctrl_z { i2c4_pins_z_mx: i2c4_mx-0 { pins { pinmux = , /* I2C4_SCL */ ; /* I2C4_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; /* USER CODE BEGIN pinctrl_z */ /* USER CODE END pinctrl_z */ }; &rcc { st,hsi-cal; st,csi-cal; st,cal-sec = <60>; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P CLK_MCU_PLL3P CLK_PLL12_HSE CLK_PLL3_HSE CLK_PLL4_HSE CLK_RTC_LSE CLK_MCO1_DISABLED CLK_MCO2_DISABLED >; st,clkdiv = < 1 /*MPU*/ 0 /*AXI*/ 0 /*MCU*/ 1 /*APB1*/ 1 /*APB2*/ 1 /*APB3*/ 1 /*APB4*/ 2 /*APB5*/ 23 /*RTC*/ 0 /*MCO1*/ 0 /*MCO2*/ >; st,pkcs = < CLK_CKPER_HSE CLK_FMC_ACLK CLK_QSPI_ACLK CLK_ETH_DISABLED CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE CLK_USBPHY_HSE CLK_SPI2S1_PLL3Q CLK_SPI2S23_PLL3Q CLK_SPI45_HSI CLK_SPI6_HSI CLK_I2C46_HSI CLK_SDMMC3_PLL4P CLK_USBO_USBPHY CLK_ADC_CKPER CLK_CEC_LSE CLK_I2C12_HSI CLK_I2C35_HSI CLK_UART1_HSI CLK_UART24_HSI CLK_UART35_HSI CLK_UART6_HSI CLK_UART78_HSI CLK_SPDIF_PLL4P CLK_FDCAN_PLL4R CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q CLK_SAI4_PLL3Q CLK_RNG1_LSI CLK_RNG2_LSI CLK_LPTIM1_PCLK1 CLK_LPTIM23_PCLK3 CLK_LPTIM45_LSE >; /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; reg = <1>; cfg = <2 65 1 0 0 PQR(1,1,1)>; frac = <0x1400>; }; /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ pll3: st,pll@2 { compatible = "st,stm32mp1-pll"; reg = <2>; cfg = <1 33 1 16 36 PQR(1,1,1)>; frac = <0x1a04>; }; /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; cfg = <3 98 5 7 7 PQR(1,1,1)>; }; }; &bsec{ board_id:board_id@ec{ reg = <0xec 0x4>; st,non-secure-otp; }; }; &cryp1{ status = "okay"; /* USER CODE BEGIN cryp1 */ /* USER CODE END cryp1 */ }; &etzpc{ st,decprot = < DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_S_RW, DECPROT_LOCK) DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_S_RW, DECPROT_LOCK) DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_LOCK) DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_LOCK) DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_LOCK) >; secure-status = "okay"; }; &hash1{ status = "okay"; }; &i2c4{ pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_z_mx>; status = "okay"; secure-status = "okay"; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; pmic:stpmic@33{ compatible = "st,stpmic1"; reg = <0x33>; interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; status = "okay"; secure-status = "okay"; regulators{ compatible = "st,stpmic1-regulators"; buck1-supply = <&vin>; buck2-supply = <&vin>; buck3-supply = <&vin>; buck4-supply = <&vin>; ldo1-supply = <&v3v3>; ldo2-supply = <&vin>; ldo3-supply = <&vdd_ddr>; ldo4-supply = <&vin>; ldo5-supply = <&vin>; ldo6-supply = <&v3v3>; vref_ddr-supply = <&vin>; boost-supply = <&vin>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; vddcore:buck1{ regulator-name = "vddcore"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; lp-stop{ regulator-on-in-suspend; regulator-suspend-microvolt = <1200000>; }; standby-ddr-sr{ regulator-off-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; vdd_ddr:buck2{ regulator-name = "vdd_ddr"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; lp-stop{ regulator-suspend-microvolt = <1350000>; regulator-on-in-suspend; }; standby-ddr-sr{ regulator-suspend-microvolt = <1350000>; regulator-on-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; vdd:buck3{ regulator-name = "vdd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; st,mask-reset; regulator-initial-mode = <0>; regulator-over-current-protection; lp-stop{ regulator-suspend-microvolt = <3300000>; regulator-on-in-suspend; }; standby-ddr-sr{ regulator-suspend-microvolt = <3300000>; regulator-on-in-suspend; }; standby-ddr-off{ regulator-suspend-microvolt = <3300000>; regulator-on-in-suspend; }; }; v3v3:buck4{ regulator-name = "v3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-over-current-protection; regulator-initial-mode = <0>; lp-stop{ regulator-suspend-microvolt = <3300000>; regulator-on-in-suspend; }; standby-ddr-sr{ regulator-off-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; v1v8_audio:ldo1{ regulator-name = "v1v8_audio"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; standby-ddr-sr{ regulator-off-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; v3v3_hdmi:ldo2{ regulator-name = "v3v3_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; standby-ddr-sr{ regulator-off-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; vtt_ddr:ldo3{ regulator-name = "vtt_ddr"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection; lp-stop{ regulator-off-in-suspend; }; standby-ddr-sr{ regulator-off-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; vdd_usb:ldo4{ regulator-name = "vdd_usb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; standby-ddr-sr{ regulator-on-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; vdda:ldo5{ regulator-name = "vdda"; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; regulator-boot-on; standby-ddr-sr{ regulator-off-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; v1v2_hdmi:ldo6{ regulator-name = "v1v2_hdmi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; standby-ddr-sr{ regulator-off-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; vref_ddr:vref_ddr{ regulator-name = "vref_ddr"; regulator-always-on; regulator-over-current-protection; lp-stop{ regulator-on-in-suspend; }; standby-ddr-sr{ regulator-on-in-suspend; }; standby-ddr-off{ regulator-off-in-suspend; }; }; bst_out:boost{ regulator-name = "bst_out"; }; vbus_otg:pwr_sw1{ regulator-name = "vbus_otg"; }; vbus_sw:pwr_sw2{ regulator-name = "vbus_sw"; regulator-active-discharge = <1>; }; }; }; /* USER CODE END i2c4 */ }; &iwdg2{ status = "okay"; secure-status = "okay"; timeout-sec = <32>; }; &rcc{ status = "okay"; secure-status = "okay"; /* USER CODE BEGIN rcc */ /* USER CODE END rcc */ }; &rng1{ status = "okay"; secure-status = "okay"; }; &rtc{ status = "okay"; secure-status = "okay"; }; &sdmmc1{ pinctrl-names = "default"; pinctrl-0 = <&sdmmc1_pins_mx>; status = "okay"; disable-wp; st,neg-edge; bus-width = <4>; vmmc-supply = <&v3v3>; }; &tamp{ status = "okay"; secure-status = "okay"; /* USER CODE BEGIN tamp */ /* USER CODE END tamp */ }; &uart4{ pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_mx>; status = "okay"; }; &usbotg_hs{ status = "okay"; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; usb-role-switch; }; &usbphyc{ status = "okay"; }; &usbphyc_port0{ phy-supply = <&vdd_usb>; }; &usbphyc_port1{ phy-supply = <&vdd_usb>; }; &cpu0{ cpu-supply = <&vddcore>; }; &cpu1{ cpu-supply = <&vddcore>; }; &pwr_regulators { system_suspend_supported_soc_modes = < STM32_PM_CSLEEP_RUN STM32_PM_CSTOP_ALLOW_LP_STOP STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR >; system_off_soc_mode = ; vdd-supply = <&vdd>; vdd_3v3_usbfs-supply = <&vdd_usb>; }; &nvmem_layout{ nvmem-cells = <&cfg0_otp>, <&part_number_otp>, <&monotonic_otp>, <&nand_otp>, <&uid_otp>, <&package_otp>, <&hw2_otp>, <&pkh_otp>, <&board_id>; nvmem-cell-names = "cfg0_otp", "part_number_otp", "monotonic_otp", "nand_otp", "uid_otp", "package_otp", "hw2_otp", "pkh_otp", "board_id"; }; &timers15{ secure-status = "okay"; st,hsi-cal-input = <7>; st,csi-cal-input = <8>; };