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@@ -1,375 +0,0 @@
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-From 4a6a8a9e87e2de4acd37a9de44617d9b773b0b7c Mon Sep 17 00:00:00 2001
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-From: Peter Maydell <peter.maydell@linaro.org>
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-Date: Fri, 1 Nov 2024 14:28:44 +0000
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-Subject: [PATCH] Revert "target/arm: Fix usage of MMU indexes when EL3 is
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- AArch32"
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-
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-This reverts commit 4c2c0474693229c1f533239bb983495c5427784d.
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-
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-This commit tried to fix a problem with our usage of MMU indexes when
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-EL3 is AArch32, using what it described as a "more complicated
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-approach" where we share the same MMU index values for Secure PL1&0
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-and NonSecure PL1&0. In theory this should work, but the change
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-didn't account for (at least) two things:
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-
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-(1) The design change means we need to flush the TLBs at any point
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-where the CPU state flips from one to the other. We already flush
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-the TLB when SCR.NS is changed, but we don't flush the TLB when we
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-take an exception from NS PL1&0 into Mon or when we return from Mon
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-to NS PL1&0, and the commit didn't add any code to do that.
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-
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-(2) The ATS12NS* address translate instructions allow Mon code (which
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-is Secure) to do a stage 1+2 page table walk for NS. I thought this
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-was OK because do_ats_write() does a page table walk which doesn't
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-use the TLBs, so because it can pass both the MMU index and also an
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-ARMSecuritySpace argument we can tell the table walk that we want NS
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-stage1+2, not S. But that means that all the code within the ptw
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-that needs to find e.g. the regime EL cannot do so only with an
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-mmu_idx -- all these functions like regime_sctlr(), regime_el(), etc
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-would need to pass both an mmu_idx and the security_space, so they
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-can tell whether this is a translation regime controlled by EL1 or
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-EL3 (and so whether to look at SCTLR.S or SCTLR.NS, etc).
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-
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-In particular, because regime_el() wasn't updated to look at the
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-ARMSecuritySpace it would return 1 even when the CPU was in Monitor
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-mode (and the controlling EL is 3). This meant that page table walks
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-in Monitor mode would look at the wrong SCTLR, TCR, etc and would
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-generally fault when they should not.
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-
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-Rather than trying to make the complicated changes needed to rescue
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-the design of 4c2c04746932, we revert it in order to instead take the
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-route that that commit describes as "the most straightforward" fix,
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-where we add new MMU indexes EL30_0, EL30_3, EL30_3_PAN to correspond
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-to "Secure PL1&0 at PL0", "Secure PL1&0 at PL1", and "Secure PL1&0 at
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-PL1 with PAN".
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-
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-This revert will re-expose the "spurious alignment faults in
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-Secure PL0" issue #2326; we'll fix it again in the next commit.
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-
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-Cc: qemu-stable@nongnu.org
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-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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-Upstream-Status: Pending
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-Upstream: https://patchew.org/QEMU/20241101142845.1712482-1-peter.maydell@linaro.org
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-See: https://gitlab.com/qemu-project/qemu/-/issues/2588#note_2189338512
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-Signed-off-by: Romain Naour <romain.naour@smile.fr>
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----
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- target/arm/cpu.h | 31 +++++++++++++------------------
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- target/arm/helper.c | 34 +++++++++++-----------------------
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- target/arm/internals.h | 27 ++++-----------------------
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- target/arm/ptw.c | 6 +-----
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- target/arm/tcg/hflags.c | 4 ----
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- target/arm/tcg/translate-a64.c | 2 +-
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- target/arm/tcg/translate.c | 9 ++++-----
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- target/arm/tcg/translate.h | 2 --
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- 8 files changed, 34 insertions(+), 81 deletions(-)
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-
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-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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-index 9a3fd59562..216774f5d3 100644
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---- a/target/arm/cpu.h
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-+++ b/target/arm/cpu.h
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-@@ -2784,7 +2784,8 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
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- * + NonSecure PL1 & 0 stage 1
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- * + NonSecure PL1 & 0 stage 2
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- * + NonSecure PL2
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-- * + Secure PL1 & 0
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-+ * + Secure PL0
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-+ * + Secure PL1
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- * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
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- *
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- * For QEMU, an mmu_idx is not quite the same as a translation regime because:
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-@@ -2802,39 +2803,37 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
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- * The only use of stage 2 translations is either as part of an s1+2
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- * lookup or when loading the descriptors during a stage 1 page table walk,
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- * and in both those cases we don't use the TLB.
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-- * 4. we want to be able to use the TLB for accesses done as part of a
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-+ * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
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-+ * translation regimes, because they map reasonably well to each other
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-+ * and they can't both be active at the same time.
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-+ * 5. we want to be able to use the TLB for accesses done as part of a
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- * stage1 page table walk, rather than having to walk the stage2 page
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- * table over and over.
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-- * 5. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
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-+ * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
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- * Never (PAN) bit within PSTATE.
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-- * 6. we fold together most secure and non-secure regimes for A-profile,
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-+ * 7. we fold together most secure and non-secure regimes for A-profile,
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- * because there are no banked system registers for aarch64, so the
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- * process of switching between secure and non-secure is
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- * already heavyweight.
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-- * 7. we cannot fold together Stage 2 Secure and Stage 2 NonSecure,
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-+ * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure,
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- * because both are in use simultaneously for Secure EL2.
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- *
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- * This gives us the following list of cases:
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- *
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-- * EL0 EL1&0 stage 1+2 (or AArch32 PL0 PL1&0 stage 1+2)
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-- * EL1 EL1&0 stage 1+2 (or AArch32 PL1 PL1&0 stage 1+2)
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-- * EL1 EL1&0 stage 1+2 +PAN (or AArch32 PL1 PL1&0 stage 1+2 +PAN)
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-+ * EL0 EL1&0 stage 1+2 (aka NS PL0)
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-+ * EL1 EL1&0 stage 1+2 (aka NS PL1)
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-+ * EL1 EL1&0 stage 1+2 +PAN
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- * EL0 EL2&0
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- * EL2 EL2&0
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- * EL2 EL2&0 +PAN
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- * EL2 (aka NS PL2)
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-- * EL3 (not used when EL3 is AArch32)
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-+ * EL3 (aka S PL1)
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- * Stage2 Secure
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- * Stage2 NonSecure
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- * plus one TLB per Physical address space: S, NS, Realm, Root
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- *
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- * for a total of 14 different mmu_idx.
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- *
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-- * Note that when EL3 is AArch32, the usage is potentially confusing
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-- * because the MMU indexes are named for their AArch64 use, so code
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-- * using the ARMMMUIdx_E10_1 might be at EL3, not EL1. This is because
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-- * Secure PL1 is always at EL3.
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-- *
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- * R profile CPUs have an MPU, but can use the same set of MMU indexes
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- * as A profile. They only need to distinguish EL0 and EL1 (and
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- * EL2 for cores like the Cortex-R52).
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-@@ -3127,10 +3126,6 @@ FIELD(TBFLAG_A32, NS, 10, 1)
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- * This requires an SME trap from AArch32 mode when using NEON.
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- */
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- FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
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--/*
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-- * Indicates whether we are in the Secure PL1&0 translation regime
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-- */
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--FIELD(TBFLAG_A32, S_PL1_0, 12, 1)
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-
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- /*
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- * Bit usage when in AArch32 state, for M-profile only.
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-diff --git a/target/arm/helper.c b/target/arm/helper.c
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-index 0a582c1cd3..8fb4b474e8 100644
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---- a/target/arm/helper.c
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-+++ b/target/arm/helper.c
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-@@ -3700,7 +3700,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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- */
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- format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
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-
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-- if (arm_feature(env, ARM_FEATURE_EL2) && !arm_aa32_secure_pl1_0(env)) {
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-+ if (arm_feature(env, ARM_FEATURE_EL2)) {
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- if (mmu_idx == ARMMMUIdx_E10_0 ||
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- mmu_idx == ARMMMUIdx_E10_1 ||
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- mmu_idx == ARMMMUIdx_E10_1_PAN) {
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-@@ -3774,11 +3774,13 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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- case 0:
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- /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
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- switch (el) {
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-+ case 3:
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-+ mmu_idx = ARMMMUIdx_E3;
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-+ break;
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- case 2:
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- g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */
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- /* fall through */
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- case 1:
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-- case 3:
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- if (ri->crm == 9 && arm_pan_enabled(env)) {
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- mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
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- } else {
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-@@ -11859,11 +11861,8 @@ void arm_cpu_do_interrupt(CPUState *cs)
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-
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- uint64_t arm_sctlr(CPUARMState *env, int el)
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- {
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-- if (arm_aa32_secure_pl1_0(env)) {
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-- /* In Secure PL1&0 SCTLR_S is always controlling */
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-- el = 3;
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-- } else if (el == 0) {
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-- /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
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-+ /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
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-+ if (el == 0) {
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- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
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- el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1;
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- }
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-@@ -12523,12 +12522,8 @@ int fp_exception_el(CPUARMState *env, int cur_el)
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- return 0;
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- }
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-
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--/*
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-- * Return the exception level we're running at if this is our mmu_idx.
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-- * s_pl1_0 should be true if this is the AArch32 Secure PL1&0 translation
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-- * regime.
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-- */
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--int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx, bool s_pl1_0)
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-+/* Return the exception level we're running at if this is our mmu_idx */
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-+int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
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- {
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- if (mmu_idx & ARM_MMU_IDX_M) {
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- return mmu_idx & ARM_MMU_IDX_M_PRIV;
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-@@ -12540,7 +12535,7 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx, bool s_pl1_0)
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- return 0;
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- case ARMMMUIdx_E10_1:
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- case ARMMMUIdx_E10_1_PAN:
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-- return s_pl1_0 ? 3 : 1;
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-+ return 1;
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- case ARMMMUIdx_E2:
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- case ARMMMUIdx_E20_2:
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- case ARMMMUIdx_E20_2_PAN:
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-@@ -12578,15 +12573,6 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
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- idx = ARMMMUIdx_E10_0;
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- }
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- break;
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-- case 3:
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-- /*
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-- * AArch64 EL3 has its own translation regime; AArch32 EL3
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-- * uses the Secure PL1&0 translation regime.
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-- */
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-- if (arm_el_is_aa64(env, 3)) {
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-- return ARMMMUIdx_E3;
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-- }
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-- /* fall through */
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- case 1:
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- if (arm_pan_enabled(env)) {
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- idx = ARMMMUIdx_E10_1_PAN;
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-@@ -12606,6 +12592,8 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
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- idx = ARMMMUIdx_E2;
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- }
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- break;
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-+ case 3:
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-+ return ARMMMUIdx_E3;
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- default:
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- g_assert_not_reached();
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- }
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-diff --git a/target/arm/internals.h b/target/arm/internals.h
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-index 38545552d0..47624318c2 100644
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---- a/target/arm/internals.h
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-+++ b/target/arm/internals.h
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-@@ -275,20 +275,6 @@ FIELD(CNTHCTL, CNTPMASK, 19, 1)
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- #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
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- #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
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-
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--/**
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-- * arm_aa32_secure_pl1_0(): Return true if in Secure PL1&0 regime
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-- *
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-- * Return true if the CPU is in the Secure PL1&0 translation regime.
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-- * This requires that EL3 exists and is AArch32 and we are currently
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-- * Secure. If this is the case then the ARMMMUIdx_E10* apply and
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-- * mean we are in EL3, not EL1.
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-- */
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--static inline bool arm_aa32_secure_pl1_0(CPUARMState *env)
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--{
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-- return arm_feature(env, ARM_FEATURE_EL3) &&
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-- !arm_el_is_aa64(env, 3) && arm_is_secure(env);
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--}
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--
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- /**
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- * raise_exception: Raise the specified exception.
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- * Raise a guest exception with the specified value, syndrome register
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-@@ -822,12 +808,7 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
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- return mmu_idx | ARM_MMU_IDX_A;
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- }
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-
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--/**
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-- * Return the exception level we're running at if our current MMU index
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-- * is @mmu_idx. @s_pl1_0 should be true if this is the AArch32
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-- * Secure PL1&0 translation regime.
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-- */
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--int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx, bool s_pl1_0);
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-+int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
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-
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- /* Return the MMU index for a v7M CPU in the specified security state */
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- ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
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-@@ -922,11 +903,11 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
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- return 3;
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- case ARMMMUIdx_E10_0:
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- case ARMMMUIdx_Stage1_E0:
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-- case ARMMMUIdx_E10_1:
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-- case ARMMMUIdx_E10_1_PAN:
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-+ return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3;
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- case ARMMMUIdx_Stage1_E1:
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- case ARMMMUIdx_Stage1_E1_PAN:
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-- return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3;
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-+ case ARMMMUIdx_E10_1:
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-+ case ARMMMUIdx_E10_1_PAN:
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- case ARMMMUIdx_MPrivNegPri:
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- case ARMMMUIdx_MUserNegPri:
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- case ARMMMUIdx_MPriv:
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-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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-index 26e670290f..20ab736793 100644
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---- a/target/arm/ptw.c
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-+++ b/target/arm/ptw.c
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-@@ -3576,11 +3576,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address,
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- case ARMMMUIdx_Stage1_E1:
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- case ARMMMUIdx_Stage1_E1_PAN:
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- case ARMMMUIdx_E2:
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-- if (arm_aa32_secure_pl1_0(env)) {
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-- ss = ARMSS_Secure;
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-- } else {
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-- ss = arm_security_space_below_el3(env);
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-- }
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-+ ss = arm_security_space_below_el3(env);
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- break;
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- case ARMMMUIdx_Stage2:
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- /*
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-diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
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-index bab7822ef6..f03977b4b0 100644
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---- a/target/arm/tcg/hflags.c
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-+++ b/target/arm/tcg/hflags.c
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-@@ -198,10 +198,6 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
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- DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
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- }
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-
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-- if (arm_aa32_secure_pl1_0(env)) {
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-- DP_TBFLAG_A32(flags, S_PL1_0, 1);
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-- }
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--
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- return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
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- }
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-
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-diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
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-index 4684e7eb6e..bc2d64e883 100644
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---- a/target/arm/tcg/translate-a64.c
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-+++ b/target/arm/tcg/translate-a64.c
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-@@ -11979,7 +11979,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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- dc->tbii = EX_TBFLAG_A64(tb_flags, TBII);
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- dc->tbid = EX_TBFLAG_A64(tb_flags, TBID);
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- dc->tcma = EX_TBFLAG_A64(tb_flags, TCMA);
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-- dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx, false);
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-+ dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
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- #if !defined(CONFIG_USER_ONLY)
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- dc->user = (dc->current_el == 0);
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- #endif
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-diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
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-index e2748ff2bb..c5bc691d92 100644
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---- a/target/arm/tcg/translate.c
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-+++ b/target/arm/tcg/translate.c
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-@@ -7546,6 +7546,10 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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-
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- core_mmu_idx = EX_TBFLAG_ANY(tb_flags, MMUIDX);
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- dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx);
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-+ dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
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-+#if !defined(CONFIG_USER_ONLY)
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-+ dc->user = (dc->current_el == 0);
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-+#endif
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- dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
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- dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
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- dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
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-@@ -7576,12 +7580,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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- }
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- dc->sme_trap_nonstreaming =
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- EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING);
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-- dc->s_pl1_0 = EX_TBFLAG_A32(tb_flags, S_PL1_0);
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- }
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-- dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx, dc->s_pl1_0);
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--#if !defined(CONFIG_USER_ONLY)
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-- dc->user = (dc->current_el == 0);
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--#endif
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- dc->lse2 = false; /* applies only to aarch64 */
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- dc->cp_regs = cpu->cp_regs;
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- dc->features = env->features;
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-diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
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-index 3f0e9ceaa3..01c217f4a4 100644
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---- a/target/arm/tcg/translate.h
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-+++ b/target/arm/tcg/translate.h
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-@@ -165,8 +165,6 @@ typedef struct DisasContext {
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- uint8_t gm_blocksize;
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- /* True if the current insn_start has been updated. */
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- bool insn_start_updated;
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-- /* True if this is the AArch32 Secure PL1&0 translation regime */
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-- bool s_pl1_0;
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- /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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- int c15_cpar;
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- /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */
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---
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-2.45.0
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-
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Romain Naour