package/riscv-isa-sim: new package

Spike, the RISC-V ISA Simulator, implements a functional model of one
or more RISC-V harts.

The host package provides an alternative solution to qemu.

https://github.com/riscv-software-src/riscv-isa-sim

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>

DEVELOPERS

@@ -1599,6 +1599,7 @@ F:	package/glslsandbox-player/
 F:	package/ptm2human/
 F:	package/python-distro/
 F:	package/python-pyalsa/
+F:	package/riscv-isa-sim/
 
 N:	Julien Viard de Galbert <julien@vdg.name>
 F:	package/dieharder/

package/Config.in.host

@@ -78,6 +78,7 @@ menu "Host utilities"
 	source "package/qoriq-rcw/Config.in.host"
 	source "package/raspberrypi-usbboot/Config.in.host"
 	source "package/rauc/Config.in.host"
+	source "package/riscv-isa-sim/Config.in.host"
 	source "package/rustc/Config.in.host"
 	source "package/s6-rc/Config.in.host"
 	source "package/sam-ba/Config.in.host"

package/riscv-isa-sim/0001-riscv-disable-precompiled-headers.patch

@@ -0,0 +1,34 @@
+From 980d5143089bf32ef8a6dfdf1bb9e9fe92fa7bf5 Mon Sep 17 00:00:00 2001
+From: Julien Olivain <ju.o@free.fr>
+Date: Sun, 9 Jan 2022 13:38:48 +0100
+Subject: [PATCH] riscv: disable precompiled headers
+
+While precompiling header, some toolchains fail with the message:
+
+    /path/to/toolchain/bin/ld: /path/to/sysroot/usr/lib/Scrt1.o: in function `_start':
+    (.text+0x54): undefined reference to `main'
+
+The patch totally disable precompiled headers.
+
+Signed-off-by: Julien Olivain <ju.o@free.fr>
+---
+ riscv/riscv.mk.in | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
+index 2347ce6..4f56eaf 100644
+--- a/riscv/riscv.mk.in
++++ b/riscv/riscv.mk.in
+@@ -35,9 +35,6 @@ riscv_hdrs = \
+ 
+ riscv_install_hdrs = mmio_plugin.h
+ 
+-riscv_precompiled_hdrs = \
+-	insn_template.h \
+-
+ riscv_srcs = \
+ 	processor.cc \
+ 	execute.cc \
+-- 
+2.34.1
+

package/riscv-isa-sim/Config.in.host

@@ -0,0 +1,13 @@
+config BR2_PACKAGE_HOST_RISCV_ISA_SIM
+	bool "host riscv-isa-sim"
+	depends on BR2_HOST_GCC_AT_LEAST_4_9 # C++1
+	help
+	  Spike, the RISC-V ISA Simulator, implements a functional
+	  model of one or more RISC-V harts.
+
+	  The host package provides an alternative solution to qemu.
+
+	  https://github.com/riscv-software-src/riscv-isa-sim
+
+comment "host riscv-isa-sim needs host gcc >= 4.9"
+	depends on !BR2_HOST_GCC_AT_LEAST_4_9

package/riscv-isa-sim/riscv-isa-sim.hash

@@ -0,0 +1,3 @@
+# Locally computed
+sha256  9b29c220fed1e867e3bea4b5c565f2629237d525a4d9fe1668699c4406003a1f  riscv-isa-sim-1.1.0.tar.gz
+sha256  c65e436d18972c9c4bd192494fe4870bd2e158179474975b80a3559f27631632  LICENSE

package/riscv-isa-sim/riscv-isa-sim.mk

@@ -0,0 +1,12 @@
+################################################################################
+#
+# riscv-isa-sim
+#
+################################################################################
+
+RISCV_ISA_SIM_VERSION = 1.1.0
+RISCV_ISA_SIM_SITE = $(call github,riscv-software-src,riscv-isa-sim,v$(RISCV_ISA_SIM_VERSION))
+RISCV_ISA_SIM_LICENSE = BSD-3-Clause
+RISCV_ISA_SIM_LICENSE_FILES = LICENSE
+
+$(eval $(host-autotools-package))