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@@ -0,0 +1,39 @@
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+From c6677ee92c05e3f0f22cc08e3b309a996292562f Mon Sep 17 00:00:00 2001
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+From: Neal Frager <neal.frager@amd.com>
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+Date: Fri, 13 May 2022 14:02:07 +0100
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+Subject: [PATCH 1/1] arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL
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+ configuration
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+
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+This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som.
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+
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+The Linux DP driver expects the DP to be using the following PLL config:
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+ - DP video PLL should use the VPLL (0x0)
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+ - DP audio PLL should use the RPLL (0x3)
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+ - DP system time clock PLL should use RPLL (0x3)
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+
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+Register 0xFD1A0070 configures the DP video PLL.
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+Register 0xFD1A0074 configures the DP audio PLL.
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+Register 0xFD1A007C configures the DP system time clock PLL.
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+
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+Signed-off-by: Neal Frager <neal.frager@amd.com>
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+---
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+ board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 3 +++
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+ 1 file changed, 3 insertions(+)
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+
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+diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
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+index ed025790bc..e5598807e8 100644
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+--- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
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++++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
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+@@ -74,6 +74,9 @@ static unsigned long psu_clock_init_data(void)
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+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U);
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+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
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+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
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++ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
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++ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
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++ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U);
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+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
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+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
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+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
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+--
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+2.17.1
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+
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