package/xilinx-fpgautil: new package

Add a new package to Buildroot called xilinx-fpgautil which builds the
Xilinx fpgautil script which can be used for loading FPGA bitstreams
on zynq, zynqmp and versal products at run-time.  This is a handy
application for loading FPGA bitstreams and their corresponding device
tree overlays.

An explanation of how this script can be used for each type of product
can be found on the wiki pages below.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841847/Solution+ZynqMP+PL+Programming
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1188397412/Solution+Versal+PL+Programming

In addition, the source code for xilinx-fpgautil can be found here:
https://github.com/Xilinx/meta-xilinx/blob/master/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c

The Xilinx fpgautil script can be used hand in hand with the Versal
Segmented Configuration with the following example command for
programming the pld.pdi file to the Versal FPGA:

    fpgautil -b /lib/firmware/xilinx/<design-name>_pld.pdi -o /lib/firmware/xilinx/<dtbo-name>.dtbo

Signed-off-by: Neal Frager <neal.frager@amd.com>
[Luca: build-tested only]
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
[Julien: reflow commit log]
Signed-off-by: Julien Olivain <ju.o@free.fr>

DEVELOPERS

@@ -2492,6 +2492,7 @@ F:	package/binutils-bare-metal/
 F:	package/bootgen/
 F:	package/gcc-bare-metal/
 F:	package/newlib-bare-metal/
+F:	package/xilinx-fpgautil/
 F:	toolchain/toolchain-bare-metal-buildroot/
 
 N:	Nicola Di Lieto <nicola.dilieto@gmail.com>

package/Config.in

@@ -461,6 +461,7 @@ menu "Firmware"
 	source "package/ux500-firmware/Config.in"
 	source "package/wilc-firmware/Config.in"
 	source "package/wilink-bt-firmware/Config.in"
+	source "package/xilinx-fpgautil/Config.in"
 	source "package/zd1211-firmware/Config.in"
 endmenu
 	source "package/18xx-ti-utils/Config.in"

package/xilinx-fpgautil/Config.in

@@ -0,0 +1,8 @@
+config BR2_PACKAGE_XILINX_FPGAUTIL
+	bool "xilinx-fpgautil"
+	depends on BR2_arm || BR2_aarch64
+	help
+	  Xilinx FPGA Manager Utility for zynq, zynqmp
+	  and versal products.
+
+	  https://github.com/Xilinx/meta-xilinx/blob/master/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c

package/xilinx-fpgautil/xilinx-fpgautil.hash

@@ -0,0 +1,3 @@
+# Locally calculated
+sha256  439a3681d8efa9641ab39c7645836b9ac78b2fdb36242f9bc94c1f3dfb2d9c4e  xilinx-fpgautil-xlnx-rel-v2024.2_update3.tar.gz
+sha256  89807acf2309bd285f033404ee78581602f3cd9b819a16ac2f0e5f60ff4a473e  COPYING.MIT

package/xilinx-fpgautil/xilinx-fpgautil.mk

@@ -0,0 +1,22 @@
+################################################################################
+#
+# xilinx-fpgautil
+#
+################################################################################
+
+XILINX_FPGAUTIL_VERSION = xlnx-rel-v2024.2_update3
+XILINX_FPGAUTIL_SITE = $(call github,Xilinx,meta-xilinx,$(XILINX_FPGAUTIL_VERSION))
+XILINX_FPGAUTIL_LICENSE = MIT
+XILINX_FPGAUTIL_LICENSE_FILES = COPYING.MIT
+
+define XILINX_FPGAUTIL_BUILD_CMDS
+	$(TARGET_MAKE_ENV) $(TARGET_CC) $(TARGET_LDFLAGS) \
+		$(@D)/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c \
+		-o $(@D)/fpgautil
+endef
+
+define XILINX_FPGAUTIL_INSTALL_TARGET_CMDS
+	$(INSTALL) -m 0755 -D $(@D)/fpgautil $(TARGET_DIR)/usr/bin/fpgautil
+endef
+
+$(eval $(generic-package))