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@@ -0,0 +1,2077 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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+/*//
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+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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+ */
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/clock/stm32mp1-clks.h>
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/reset/stm32mp1-resets.h>
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu0: cpu@0 {
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+ compatible = "arm,cortex-a7";
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+ device_type = "cpu";
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+ reg = <0>;
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+ clocks = <&rcc CK_MPU>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu0_opp_table>;
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+ nvmem-cells = <&part_number_otp>;
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+ nvmem-cell-names = "part_number";
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+ };
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+
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+ cpu1: cpu@1 {
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+ compatible = "arm,cortex-a7";
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+ device_type = "cpu";
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+ reg = <1>;
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+ clocks = <&rcc CK_MPU>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu0_opp_table>;
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+ };
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+ };
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+
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+ cpu0_opp_table: cpu0-opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-650000000 {
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+ opp-hz = /bits/ 64 <650000000>;
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+ opp-microvolt = <1200000>;
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+ opp-supported-hw = <0x1>;
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+ };
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt = <1350000>;
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+ opp-supported-hw = <0x2>;
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+ };
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+ };
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+
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+ arm-pmu {
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+ compatible = "arm,cortex-a7-pmu";
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+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-affinity = <&cpu0>, <&cpu1>;
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+ interrupt-parent = <&intc>;
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+ };
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+
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+ psci {
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+ compatible = "arm,psci-1.0";
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+ method = "smc";
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+ };
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+
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+ intc: interrupt-controller@a0021000 {
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+ compatible = "arm,cortex-a7-gic";
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+ #interrupt-cells = <3>;
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+ interrupt-controller;
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+ reg = <0xa0021000 0x1000>,
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+ <0xa0022000 0x2000>;
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+ };
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+
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+ timer {
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+ compatible = "arm,armv7-timer";
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+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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+ interrupt-parent = <&intc>;
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+ always-on;
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+ };
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+
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+ clocks {
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+ clk_hse: clk-hse {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <24000000>;
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+ };
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+
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+ clk_hsi: clk-hsi {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <64000000>;
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+ };
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+
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+ clk_lse: clk-lse {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <32768>;
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+ };
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+
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+ clk_lsi: clk-lsi {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <32000>;
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+ };
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+
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+ clk_csi: clk-csi {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <4000000>;
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+ };
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+
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+ clk_i2s_ckin: i2s_ckin {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <0>;
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+ };
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+
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+ clk_dsi_phy: ck_dsi_phy {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <0>;
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+ };
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+ };
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+
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+ pm_domain {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32mp157c-pd";
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+
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+ pd_core_ret: core-ret-power-domain@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+ #power-domain-cells = <0>;
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+ label = "CORE-RETENTION";
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+
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+ pd_core: core-power-domain@2 {
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+ reg = <2>;
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+ #power-domain-cells = <0>;
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+ label = "CORE";
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+ };
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+ };
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+ };
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+
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+ thermal-zones {
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+ cpu_thermal: cpu-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&dts>;
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+
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+ trips {
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+ cpu-crit {
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+ temperature = <120000>;
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+ hysteresis = <0>;
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+ type = "critical";
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+ };
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+ };
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+
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+ cooling-maps {
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+ };
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+ };
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+ };
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+
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+ reboot {
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+ compatible = "syscon-reboot";
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+ regmap = <&rcc>;
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+ offset = <0x404>;
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+ mask = <0x1>;
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+ };
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+
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+ replicator {
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+ /*
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+ * non-configurable replicators don't show up on the
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+ * AMBA bus. As such no need to add "arm,primecell"
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+ */
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+ compatible = "arm,coresight-replicator";
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+ clocks = <&rcc CK_TRACE>;
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+ clock-names = "apb_pclk";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ /* replicator output ports */
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+ port@0 {
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+ reg = <0>;
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+ replicator_out_port0: endpoint {
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+ remote-endpoint = <&funnel_in_port4>;
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+ };
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+ };
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+ };
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+ };
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+
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+ soc {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ interrupt-parent = <&intc>;
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+ ranges;
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+
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+ timers2: timer@40000000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-timers";
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+ reg = <0x40000000 0x400>;
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+ clocks = <&rcc TIM2_K>;
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+ clock-names = "int";
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+ dmas = <&dmamux1 18 0x400 0x5>,
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+ <&dmamux1 19 0x400 0x5>,
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+ <&dmamux1 20 0x400 0x5>,
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+ <&dmamux1 21 0x400 0x5>,
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+ <&dmamux1 22 0x400 0x5>;
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+ dma-names = "ch1", "ch2", "ch3", "ch4", "up";
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+ status = "disabled";
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+
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+ pwm {
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+ compatible = "st,stm32-pwm";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ timer@1 {
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+ compatible = "st,stm32h7-timer-trigger";
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+ reg = <1>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ timers3: timer@40001000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-timers";
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+ reg = <0x40001000 0x400>;
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+ clocks = <&rcc TIM3_K>;
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+ clock-names = "int";
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+ dmas = <&dmamux1 23 0x400 0x5>,
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+ <&dmamux1 24 0x400 0x5>,
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+ <&dmamux1 25 0x400 0x5>,
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+ <&dmamux1 26 0x400 0x5>,
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+ <&dmamux1 27 0x400 0x5>,
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+ <&dmamux1 28 0x400 0x5>;
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+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
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+ status = "disabled";
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+
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+ pwm {
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+ compatible = "st,stm32-pwm";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ timer@2 {
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+ compatible = "st,stm32h7-timer-trigger";
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+ reg = <2>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ timers4: timer@40002000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-timers";
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+ reg = <0x40002000 0x400>;
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+ clocks = <&rcc TIM4_K>;
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+ clock-names = "int";
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+ dmas = <&dmamux1 29 0x400 0x5>,
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+ <&dmamux1 30 0x400 0x5>,
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+ <&dmamux1 31 0x400 0x5>,
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+ <&dmamux1 32 0x400 0x5>;
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+ dma-names = "ch1", "ch2", "ch3", "ch4";
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+ status = "disabled";
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+
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+ pwm {
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+ compatible = "st,stm32-pwm";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ timer@3 {
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+ compatible = "st,stm32h7-timer-trigger";
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+ reg = <3>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ timers5: timer@40003000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-timers";
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+ reg = <0x40003000 0x400>;
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+ clocks = <&rcc TIM5_K>;
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+ clock-names = "int";
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+ dmas = <&dmamux1 55 0x400 0x5>,
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+ <&dmamux1 56 0x400 0x5>,
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+ <&dmamux1 57 0x400 0x5>,
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+ <&dmamux1 58 0x400 0x5>,
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+ <&dmamux1 59 0x400 0x5>,
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+ <&dmamux1 60 0x400 0x5>;
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+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
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+ status = "disabled";
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+
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+ pwm {
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+ compatible = "st,stm32-pwm";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ timer@4 {
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+ compatible = "st,stm32h7-timer-trigger";
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+ reg = <4>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ timers6: timer@40004000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-timers";
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+ reg = <0x40004000 0x400>;
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+ clocks = <&rcc TIM6_K>;
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+ clock-names = "int";
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+ dmas = <&dmamux1 69 0x400 0x5>;
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+ dma-names = "up";
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+ status = "disabled";
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+
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+ timer@5 {
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+ compatible = "st,stm32h7-timer-trigger";
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+ reg = <5>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ timers7: timer@40005000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-timers";
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+ reg = <0x40005000 0x400>;
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+ clocks = <&rcc TIM7_K>;
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+ clock-names = "int";
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+ dmas = <&dmamux1 70 0x400 0x5>;
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+ dma-names = "up";
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+ status = "disabled";
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+
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+ timer@6 {
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+ compatible = "st,stm32h7-timer-trigger";
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+ reg = <6>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ timers12: timer@40006000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-timers";
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+ reg = <0x40006000 0x400>;
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+ clocks = <&rcc TIM12_K>;
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+ clock-names = "int";
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+ status = "disabled";
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+
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+ pwm {
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+ compatible = "st,stm32-pwm";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ timer@11 {
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+ compatible = "st,stm32h7-timer-trigger";
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+ reg = <11>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ timers13: timer@40007000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-timers";
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+ reg = <0x40007000 0x400>;
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+ clocks = <&rcc TIM13_K>;
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+ clock-names = "int";
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+ status = "disabled";
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+
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+ pwm {
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+ compatible = "st,stm32-pwm";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ timer@12 {
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+ compatible = "st,stm32h7-timer-trigger";
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+ reg = <12>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ timers14: timer@40008000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-timers";
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+ reg = <0x40008000 0x400>;
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+ clocks = <&rcc TIM14_K>;
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+ clock-names = "int";
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+ status = "disabled";
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+
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+ pwm {
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+ compatible = "st,stm32-pwm";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ timer@13 {
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+ compatible = "st,stm32h7-timer-trigger";
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+ reg = <13>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ lptimer1: timer@40009000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32-lptimer";
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+ reg = <0x40009000 0x400>;
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|
|
+ clocks = <&rcc LPTIM1_K>;
|
|
|
+ clock-names = "mux";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ trigger@0 {
|
|
|
+ compatible = "st,stm32-lptimer-trigger";
|
|
|
+ reg = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ counter {
|
|
|
+ compatible = "st,stm32-lptimer-counter";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ spi2: spi@4000b000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x4000b000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI2_K>;
|
|
|
+ resets = <&rcc SPI2_R>;
|
|
|
+ dmas = <&dmamux1 39 0x400 0x01>,
|
|
|
+ <&dmamux1 40 0x400 0x01>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2s2: audio-controller@4000b000 {
|
|
|
+ compatible = "st,stm32h7-i2s";
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ reg = <0x4000b000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 39 0x400 0x01>,
|
|
|
+ <&dmamux1 40 0x400 0x01>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi3: spi@4000c000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x4000c000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI3_K>;
|
|
|
+ resets = <&rcc SPI3_R>;
|
|
|
+ dmas = <&dmamux1 61 0x400 0x01>,
|
|
|
+ <&dmamux1 62 0x400 0x01>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2s3: audio-controller@4000c000 {
|
|
|
+ compatible = "st,stm32h7-i2s";
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ reg = <0x4000c000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 61 0x400 0x01>,
|
|
|
+ <&dmamux1 62 0x400 0x01>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spdifrx: audio-controller@4000d000 {
|
|
|
+ compatible = "st,stm32h7-spdifrx";
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ reg = <0x4000d000 0x400>;
|
|
|
+ clocks = <&rcc SPDIF_K>;
|
|
|
+ clock-names = "kclk";
|
|
|
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 93 0x400 0x01>,
|
|
|
+ <&dmamux1 94 0x400 0x01>;
|
|
|
+ dma-names = "rx", "rx-ctrl";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ usart2: serial@4000e000 {
|
|
|
+ compatible = "st,stm32h7-uart";
|
|
|
+ reg = <0x4000e000 0x400>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 27 1>;
|
|
|
+ clocks = <&rcc USART2_K>;
|
|
|
+ resets = <&rcc USART2_R>;
|
|
|
+ wakeup-source;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ dmas = <&dmamux1 43 0x400 0x21>,
|
|
|
+ <&dmamux1 44 0x400 0x1>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ usart3: serial@4000f000 {
|
|
|
+ compatible = "st,stm32h7-uart";
|
|
|
+ reg = <0x4000f000 0x400>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 28 1>;
|
|
|
+ clocks = <&rcc USART3_K>;
|
|
|
+ resets = <&rcc USART3_R>;
|
|
|
+ wakeup-source;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ dmas = <&dmamux1 45 0x400 0x21>,
|
|
|
+ <&dmamux1 46 0x400 0x1>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ uart4: serial@40010000 {
|
|
|
+ compatible = "st,stm32h7-uart";
|
|
|
+ reg = <0x40010000 0x400>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 30 1>;
|
|
|
+ clocks = <&rcc UART4_K>;
|
|
|
+ resets = <&rcc UART4_R>;
|
|
|
+ wakeup-source;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ dmas = <&dmamux1 63 0x400 0x21>,
|
|
|
+ <&dmamux1 64 0x400 0x1>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ uart5: serial@40011000 {
|
|
|
+ compatible = "st,stm32h7-uart";
|
|
|
+ reg = <0x40011000 0x400>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 31 1>;
|
|
|
+ clocks = <&rcc UART5_K>;
|
|
|
+ resets = <&rcc UART5_R>;
|
|
|
+ wakeup-source;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ dmas = <&dmamux1 65 0x400 0x21>,
|
|
|
+ <&dmamux1 66 0x400 0x1>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c1: i2c@40012000 {
|
|
|
+ compatible = "st,stm32f7-i2c";
|
|
|
+ reg = <0x40012000 0x400>;
|
|
|
+ interrupt-names = "event", "error", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 21 1>;
|
|
|
+ clocks = <&rcc I2C1_K>;
|
|
|
+ resets = <&rcc I2C1_R>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ dmas = <&dmamux1 33 0x400 0x05>,
|
|
|
+ <&dmamux1 34 0x400 0x05>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x1>;
|
|
|
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x1>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c2: i2c@40013000 {
|
|
|
+ compatible = "st,stm32f7-i2c";
|
|
|
+ reg = <0x40013000 0x400>;
|
|
|
+ interrupt-names = "event", "error", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 22 1>;
|
|
|
+ clocks = <&rcc I2C2_K>;
|
|
|
+ resets = <&rcc I2C2_R>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ dmas = <&dmamux1 35 0x400 0x05>,
|
|
|
+ <&dmamux1 36 0x400 0x05>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
|
|
|
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c3: i2c@40014000 {
|
|
|
+ compatible = "st,stm32f7-i2c";
|
|
|
+ reg = <0x40014000 0x400>;
|
|
|
+ interrupt-names = "event", "error", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 23 1>;
|
|
|
+ clocks = <&rcc I2C3_K>;
|
|
|
+ resets = <&rcc I2C3_R>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ dmas = <&dmamux1 73 0x400 0x05>,
|
|
|
+ <&dmamux1 74 0x400 0x05>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
|
|
|
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x4>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c5: i2c@40015000 {
|
|
|
+ compatible = "st,stm32f7-i2c";
|
|
|
+ reg = <0x40015000 0x400>;
|
|
|
+ interrupt-names = "event", "error", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 25 1>;
|
|
|
+ clocks = <&rcc I2C5_K>;
|
|
|
+ resets = <&rcc I2C5_R>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ dmas = <&dmamux1 115 0x400 0x05>,
|
|
|
+ <&dmamux1 116 0x400 0x05>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
|
|
|
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x10>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ cec: cec@40016000 {
|
|
|
+ compatible = "st,stm32-cec";
|
|
|
+ reg = <0x40016000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc CEC_K>, <&rcc CEC>;
|
|
|
+ clock-names = "cec", "hdmi-cec";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dac: dac@40017000 {
|
|
|
+ compatible = "st,stm32h7-dac-core";
|
|
|
+ reg = <0x40017000 0x400>;
|
|
|
+ clocks = <&rcc DAC12>;
|
|
|
+ clock-names = "pclk";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ dac1: dac@1 {
|
|
|
+ compatible = "st,stm32-dac";
|
|
|
+ #io-channels-cells = <1>;
|
|
|
+ reg = <1>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dac2: dac@2 {
|
|
|
+ compatible = "st,stm32-dac";
|
|
|
+ #io-channels-cells = <1>;
|
|
|
+ reg = <2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart7: serial@40018000 {
|
|
|
+ compatible = "st,stm32h7-uart";
|
|
|
+ reg = <0x40018000 0x400>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 32 1>;
|
|
|
+ clocks = <&rcc UART7_K>;
|
|
|
+ resets = <&rcc UART7_R>;
|
|
|
+ wakeup-source;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ dmas = <&dmamux1 79 0x400 0x21>,
|
|
|
+ <&dmamux1 80 0x400 0x1>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ uart8: serial@40019000 {
|
|
|
+ compatible = "st,stm32h7-uart";
|
|
|
+ reg = <0x40019000 0x400>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 33 1>;
|
|
|
+ clocks = <&rcc UART8_K>;
|
|
|
+ resets = <&rcc UART8_R>;
|
|
|
+ wakeup-source;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ dmas = <&dmamux1 81 0x400 0x21>,
|
|
|
+ <&dmamux1 82 0x400 0x1>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ timers1: timer@44000000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32-timers";
|
|
|
+ reg = <0x44000000 0x400>;
|
|
|
+ clocks = <&rcc TIM1_K>;
|
|
|
+ clock-names = "int";
|
|
|
+ dmas = <&dmamux1 11 0x400 0x5>,
|
|
|
+ <&dmamux1 12 0x400 0x5>,
|
|
|
+ <&dmamux1 13 0x400 0x5>,
|
|
|
+ <&dmamux1 14 0x400 0x5>,
|
|
|
+ <&dmamux1 15 0x400 0x5>,
|
|
|
+ <&dmamux1 16 0x400 0x5>,
|
|
|
+ <&dmamux1 17 0x400 0x5>;
|
|
|
+ dma-names = "ch1", "ch2", "ch3", "ch4",
|
|
|
+ "up", "trig", "com";
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ timer@0 {
|
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
|
+ reg = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ timers8: timer@44001000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32-timers";
|
|
|
+ reg = <0x44001000 0x400>;
|
|
|
+ clocks = <&rcc TIM8_K>;
|
|
|
+ clock-names = "int";
|
|
|
+ dmas = <&dmamux1 47 0x400 0x5>,
|
|
|
+ <&dmamux1 48 0x400 0x5>,
|
|
|
+ <&dmamux1 49 0x400 0x5>,
|
|
|
+ <&dmamux1 50 0x400 0x5>,
|
|
|
+ <&dmamux1 51 0x400 0x5>,
|
|
|
+ <&dmamux1 52 0x400 0x5>,
|
|
|
+ <&dmamux1 53 0x400 0x5>;
|
|
|
+ dma-names = "ch1", "ch2", "ch3", "ch4",
|
|
|
+ "up", "trig", "com";
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ timer@7 {
|
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
|
+ reg = <7>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ usart6: serial@44003000 {
|
|
|
+ compatible = "st,stm32h7-uart";
|
|
|
+ reg = <0x44003000 0x400>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 29 1>;
|
|
|
+ clocks = <&rcc USART6_K>;
|
|
|
+ resets = <&rcc USART6_R>;
|
|
|
+ wakeup-source;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ dmas = <&dmamux1 71 0x400 0x21>,
|
|
|
+ <&dmamux1 72 0x400 0x1>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi1: spi@44004000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x44004000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI1_K>;
|
|
|
+ resets = <&rcc SPI1_R>;
|
|
|
+ dmas = <&dmamux1 37 0x400 0x01>,
|
|
|
+ <&dmamux1 38 0x400 0x01>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2s1: audio-controller@44004000 {
|
|
|
+ compatible = "st,stm32h7-i2s";
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ reg = <0x44004000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 37 0x400 0x01>,
|
|
|
+ <&dmamux1 38 0x400 0x01>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi4: spi@44005000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x44005000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI4_K>;
|
|
|
+ resets = <&rcc SPI4_R>;
|
|
|
+ dmas = <&dmamux1 83 0x400 0x01>,
|
|
|
+ <&dmamux1 84 0x400 0x01>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ timers15: timer@44006000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32-timers";
|
|
|
+ reg = <0x44006000 0x400>;
|
|
|
+ clocks = <&rcc TIM15_K>;
|
|
|
+ clock-names = "int";
|
|
|
+ dmas = <&dmamux1 105 0x400 0x5>,
|
|
|
+ <&dmamux1 106 0x400 0x5>,
|
|
|
+ <&dmamux1 107 0x400 0x5>,
|
|
|
+ <&dmamux1 108 0x400 0x5>;
|
|
|
+ dma-names = "ch1", "up", "trig", "com";
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ timer@14 {
|
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
|
+ reg = <14>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ timers16: timer@44007000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32-timers";
|
|
|
+ reg = <0x44007000 0x400>;
|
|
|
+ clocks = <&rcc TIM16_K>;
|
|
|
+ clock-names = "int";
|
|
|
+ dmas = <&dmamux1 109 0x400 0x5>,
|
|
|
+ <&dmamux1 110 0x400 0x5>;
|
|
|
+ dma-names = "ch1", "up";
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ timer@15 {
|
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
|
+ reg = <15>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ timers17: timer@44008000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32-timers";
|
|
|
+ reg = <0x44008000 0x400>;
|
|
|
+ clocks = <&rcc TIM17_K>;
|
|
|
+ clock-names = "int";
|
|
|
+ dmas = <&dmamux1 111 0x400 0x5>,
|
|
|
+ <&dmamux1 112 0x400 0x5>;
|
|
|
+ dma-names = "ch1", "up";
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ timer@16 {
|
|
|
+ compatible = "st,stm32h7-timer-trigger";
|
|
|
+ reg = <16>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ spi5: spi@44009000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x44009000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI5_K>;
|
|
|
+ resets = <&rcc SPI5_R>;
|
|
|
+ dmas = <&dmamux1 85 0x400 0x01>,
|
|
|
+ <&dmamux1 86 0x400 0x01>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ sai1: sai@4400a000 {
|
|
|
+ compatible = "st,stm32h7-sai";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+ ranges = <0 0x4400a000 0x400>;
|
|
|
+ reg = <0x4400a000 0x4>;
|
|
|
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ resets = <&rcc SAI1_R>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ sai1a: audio-controller@4400a004 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+
|
|
|
+ compatible = "st,stm32-sai-sub-a";
|
|
|
+ reg = <0x4 0x1c>;
|
|
|
+ clocks = <&rcc SAI1_K>;
|
|
|
+ clock-names = "sai_ck";
|
|
|
+ dmas = <&dmamux1 87 0x400 0x01>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ sai1b: audio-controller@4400a024 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "st,stm32-sai-sub-b";
|
|
|
+ reg = <0x24 0x1c>;
|
|
|
+ clocks = <&rcc SAI1_K>;
|
|
|
+ clock-names = "sai_ck";
|
|
|
+ dmas = <&dmamux1 88 0x400 0x01>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ sai2: sai@4400b000 {
|
|
|
+ compatible = "st,stm32h7-sai";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+ ranges = <0 0x4400b000 0x400>;
|
|
|
+ reg = <0x4400b000 0x4>;
|
|
|
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ resets = <&rcc SAI2_R>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ sai2a: audio-controller@4400b004 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "st,stm32-sai-sub-a";
|
|
|
+ reg = <0x4 0x1c>;
|
|
|
+ clocks = <&rcc SAI2_K>;
|
|
|
+ clock-names = "sai_ck";
|
|
|
+ dmas = <&dmamux1 89 0x400 0x01>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ sai2b: audio-controller@4400b024 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "st,stm32-sai-sub-b";
|
|
|
+ reg = <0x24 0x1c>;
|
|
|
+ clocks = <&rcc SAI2_K>;
|
|
|
+ clock-names = "sai_ck";
|
|
|
+ dmas = <&dmamux1 90 0x400 0x01>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ sai3: sai@4400c000 {
|
|
|
+ compatible = "st,stm32h7-sai";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+ ranges = <0 0x4400c000 0x400>;
|
|
|
+ reg = <0x4400c000 0x4>;
|
|
|
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ resets = <&rcc SAI3_R>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ sai3a: audio-controller@4400c004 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "st,stm32-sai-sub-a";
|
|
|
+ reg = <0x04 0x1c>;
|
|
|
+ clocks = <&rcc SAI3_K>;
|
|
|
+ clock-names = "sai_ck";
|
|
|
+ dmas = <&dmamux1 113 0x400 0x01>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ sai3b: audio-controller@4400c024 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "st,stm32-sai-sub-b";
|
|
|
+ reg = <0x24 0x1c>;
|
|
|
+ clocks = <&rcc SAI3_K>;
|
|
|
+ clock-names = "sai_ck";
|
|
|
+ dmas = <&dmamux1 114 0x400 0x01>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm: dfsdm@4400d000 {
|
|
|
+ compatible = "st,stm32mp1-dfsdm";
|
|
|
+ reg = <0x4400d000 0x800>;
|
|
|
+ clocks = <&rcc DFSDM_K>;
|
|
|
+ clock-names = "dfsdm";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ dfsdm0: filter@0 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <0>;
|
|
|
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 101 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm1: filter@1 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <1>;
|
|
|
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 102 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm2: filter@2 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <2>;
|
|
|
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 103 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm3: filter@3 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <3>;
|
|
|
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 104 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm4: filter@4 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <4>;
|
|
|
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 91 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dfsdm5: filter@5 {
|
|
|
+ compatible = "st,stm32-dfsdm-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <5>;
|
|
|
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&dmamux1 92 0x400 0x01>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ m_can1: can@4400e000 {
|
|
|
+ compatible = "bosch,m_can";
|
|
|
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
|
|
+ reg-names = "m_can", "message_ram";
|
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "int0", "int1";
|
|
|
+ clocks = <&rcc FDCAN>, <&rcc FDCAN_K>;
|
|
|
+ clock-names = "hclk", "cclk";
|
|
|
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ m_can2: can@4400f000 {
|
|
|
+ compatible = "bosch,m_can";
|
|
|
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
|
|
+ reg-names = "m_can", "message_ram";
|
|
|
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "int0", "int1";
|
|
|
+ clocks = <&rcc FDCAN>, <&rcc FDCAN_K>;
|
|
|
+ clock-names = "hclk", "cclk";
|
|
|
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dma1: dma@48000000 {
|
|
|
+ compatible = "st,stm32-dma";
|
|
|
+ reg = <0x48000000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc DMA1>;
|
|
|
+ resets = <&rcc DMA1_R>;
|
|
|
+ #dma-cells = <4>;
|
|
|
+ st,mem2mem;
|
|
|
+ dma-requests = <8>;
|
|
|
+ dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>,
|
|
|
+ <&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>,
|
|
|
+ <&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>,
|
|
|
+ <&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>,
|
|
|
+ <&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>,
|
|
|
+ <&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>,
|
|
|
+ <&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>,
|
|
|
+ <&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>;
|
|
|
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
|
|
+ };
|
|
|
+
|
|
|
+ dma2: dma@48001000 {
|
|
|
+ compatible = "st,stm32-dma";
|
|
|
+ reg = <0x48001000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc DMA2>;
|
|
|
+ resets = <&rcc DMA2_R>;
|
|
|
+ #dma-cells = <4>;
|
|
|
+ st,mem2mem;
|
|
|
+ dma-requests = <8>;
|
|
|
+ dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>,
|
|
|
+ <&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>,
|
|
|
+ <&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>,
|
|
|
+ <&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>,
|
|
|
+ <&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>,
|
|
|
+ <&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>,
|
|
|
+ <&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>,
|
|
|
+ <&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>;
|
|
|
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
|
|
+ };
|
|
|
+
|
|
|
+ dmamux1: dma-router@48002000 {
|
|
|
+ compatible = "st,stm32h7-dmamux";
|
|
|
+ reg = <0x48002000 0x1c>;
|
|
|
+ #dma-cells = <3>;
|
|
|
+ dma-requests = <128>;
|
|
|
+ dma-masters = <&dma1 &dma2>;
|
|
|
+ dma-channels = <16>;
|
|
|
+ clocks = <&rcc DMAMUX>;
|
|
|
+ resets = <&rcc DMAMUX_R>;
|
|
|
+ };
|
|
|
+
|
|
|
+ adc: adc@48003000 {
|
|
|
+ compatible = "st,stm32mp1-adc-core";
|
|
|
+ reg = <0x48003000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
|
|
|
+ clock-names = "bus", "adc";
|
|
|
+ interrupt-controller;
|
|
|
+ st,syscfg-vbooster = <&syscfg 0x4 0x100>;
|
|
|
+ st,syscfg-vbooster-clr = <&syscfg 0x44 0x100>;
|
|
|
+ st,syscfg-anaswvdd = <&syscfg 0x4 0x200>;
|
|
|
+ st,syscfg-anaswvdd-clr = <&syscfg 0x44 0x200>;
|
|
|
+ #interrupt-cells = <1>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ adc1: adc@0 {
|
|
|
+ compatible = "st,stm32mp1-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <0x0>;
|
|
|
+ interrupt-parent = <&adc>;
|
|
|
+ interrupts = <0>;
|
|
|
+ dmas = <&dmamux1 9 0x400 0x05>;
|
|
|
+ dma-names = "rx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ adc2: adc@100 {
|
|
|
+ compatible = "st,stm32mp1-adc";
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <0x100>;
|
|
|
+ interrupt-parent = <&adc>;
|
|
|
+ interrupts = <1>;
|
|
|
+ dmas = <&dmamux1 10 0x400 0x05>;
|
|
|
+ dma-names = "rx";
|
|
|
+ /* temperature sensor */
|
|
|
+ st,adc-channels = <12>;
|
|
|
+ st,min-sample-time-nsecs = <10000>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ jadc1: jadc@0 {
|
|
|
+ compatible = "st,stm32mp1-adc";
|
|
|
+ st,injected;
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <0x0>;
|
|
|
+ interrupt-parent = <&adc>;
|
|
|
+ interrupts = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ jadc2: jadc@100 {
|
|
|
+ compatible = "st,stm32mp1-adc";
|
|
|
+ st,injected;
|
|
|
+ #io-channel-cells = <1>;
|
|
|
+ reg = <0x100>;
|
|
|
+ interrupt-parent = <&adc>;
|
|
|
+ interrupts = <4>;
|
|
|
+ /* temperature sensor */
|
|
|
+ st,adc-channels = <12>;
|
|
|
+ st,min-sample-time-nsecs = <10000>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ adc_temp: temp {
|
|
|
+ compatible = "st,stm32mp1-adc-temp";
|
|
|
+ io-channels = <&adc2 12>;
|
|
|
+ nvmem-cells = <&ts_cal1>, <&ts_cal2>;
|
|
|
+ nvmem-cell-names = "ts_cal1", "ts_cal2";
|
|
|
+ #io-channel-cells = <0>;
|
|
|
+ #thermal-sensor-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ sdmmc3: sdmmc@48004000 {
|
|
|
+ compatible = "arm,pl18x", "arm,primecell";
|
|
|
+ arm,primecell-periphid = <0x00253180>;
|
|
|
+ reg = <0x48004000 0x400>, <0x48005000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "cmd_irq";
|
|
|
+ clocks = <&rcc SDMMC3_K>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+ resets = <&rcc SDMMC3_R>;
|
|
|
+ cap-sd-highspeed;
|
|
|
+ cap-mmc-highspeed;
|
|
|
+ max-frequency = <120000000>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ usbotg_hs: usb-otg@49000000 {
|
|
|
+ compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
|
|
+ reg = <0x49000000 0x10000>;
|
|
|
+ clocks = <&rcc USBO_K>;
|
|
|
+ clock-names = "otg";
|
|
|
+ resets = <&rcc USBO_R>;
|
|
|
+ reset-names = "dwc2";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 44 1>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ g-rx-fifo-size = <256>;
|
|
|
+ g-np-tx-fifo-size = <32>;
|
|
|
+ g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
|
|
+ dr_mode = "otg";
|
|
|
+ usb33d-supply = <&usb33>;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ wakeup-source;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ hsem: hwspinlock@4c000000 {
|
|
|
+ compatible = "st,stm32-hwspinlock";
|
|
|
+ #hwlock-cells = <1>;
|
|
|
+ reg = <0x4c000000 0x400>;
|
|
|
+ clocks = <&rcc HSEM>;
|
|
|
+ clock-names = "hsem";
|
|
|
+ status = "okay";
|
|
|
+ };
|
|
|
+
|
|
|
+ ipcc: mailbox@4c001000 {
|
|
|
+ compatible = "st,stm32mp1-ipcc";
|
|
|
+ #mbox-cells = <1>;
|
|
|
+ reg = <0x4c001000 0x400>;
|
|
|
+ st,proc-id = <0>;
|
|
|
+ interrupts-extended =
|
|
|
+ <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 61 1>;
|
|
|
+ interrupt-names = "rx", "tx", "wakeup";
|
|
|
+ clocks = <&rcc IPCC>;
|
|
|
+ wakeup-source;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dcmi: dcmi@4c006000 {
|
|
|
+ compatible = "st,stm32-dcmi";
|
|
|
+ reg = <0x4c006000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ resets = <&rcc CAMITF_R>;
|
|
|
+ clocks = <&rcc DCMI>;
|
|
|
+ clock-names = "mclk";
|
|
|
+ dmas = <&dmamux1 75 0x400 0x1d>;
|
|
|
+ dma-names = "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ rcc: rcc@50000000 {
|
|
|
+ compatible = "st,stm32mp1-rcc", "syscon";
|
|
|
+ reg = <0x50000000 0x1000>;
|
|
|
+ #clock-cells = <1>;
|
|
|
+ #reset-cells = <1>;
|
|
|
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ };
|
|
|
+
|
|
|
+ pwr: pwr@50001000 {
|
|
|
+ compatible = "st,stm32mp1-pwr", "syscon", "simple-mfd";
|
|
|
+ reg = <0x50001000 0x400>;
|
|
|
+
|
|
|
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+
|
|
|
+ interrupt-controller;
|
|
|
+ #interrupt-cells = <3>;
|
|
|
+
|
|
|
+ wakeup-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>,
|
|
|
+ <&gpioa 2 GPIO_ACTIVE_HIGH>,
|
|
|
+ <&gpioc 13 GPIO_ACTIVE_HIGH>,
|
|
|
+ <&gpioi 8 GPIO_ACTIVE_HIGH>,
|
|
|
+ <&gpioi 11 GPIO_ACTIVE_HIGH>,
|
|
|
+ <&gpioc 1 GPIO_ACTIVE_HIGH>;
|
|
|
+
|
|
|
+ pwr-regulators {
|
|
|
+ compatible = "st,stm32mp1,pwr-reg";
|
|
|
+ st,tzcr = <&rcc 0x0 0x1>;
|
|
|
+
|
|
|
+ reg11: reg11 {
|
|
|
+ regulator-name = "reg11";
|
|
|
+ regulator-min-microvolt = <1100000>;
|
|
|
+ regulator-max-microvolt = <1100000>;
|
|
|
+ };
|
|
|
+
|
|
|
+ reg18: reg18 {
|
|
|
+ regulator-name = "reg18";
|
|
|
+ regulator-min-microvolt = <1800000>;
|
|
|
+ regulator-max-microvolt = <1800000>;
|
|
|
+ };
|
|
|
+
|
|
|
+ usb33: usb33 {
|
|
|
+ regulator-name = "usb33";
|
|
|
+ regulator-min-microvolt = <3300000>;
|
|
|
+ regulator-max-microvolt = <3300000>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ exti: interrupt-controller@5000d000 {
|
|
|
+ compatible = "st,stm32mp1-exti", "syscon";
|
|
|
+ interrupt-controller;
|
|
|
+ #interrupt-cells = <2>;
|
|
|
+ reg = <0x5000d000 0x400>;
|
|
|
+ hwlocks = <&hsem 1>;
|
|
|
+
|
|
|
+ /* exti_pwr is an extra interrupt controller used for
|
|
|
+ * EXTI 55 to 60. It's mapped on pwr interrupt
|
|
|
+ * controller.
|
|
|
+ */
|
|
|
+ exti_pwr: exti-pwr {
|
|
|
+ interrupt-controller;
|
|
|
+ #interrupt-cells = <2>;
|
|
|
+ interrupt-parent = <&pwr>;
|
|
|
+ st,irq-number = <6>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ syscfg: syscon@50020000 {
|
|
|
+ compatible = "st,stm32mp157-syscfg", "syscon";
|
|
|
+ reg = <0x50020000 0x400>;
|
|
|
+ clocks = <&rcc SYSCFG>;
|
|
|
+ };
|
|
|
+
|
|
|
+ lptimer2: timer@50021000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32-lptimer";
|
|
|
+ reg = <0x50021000 0x400>;
|
|
|
+ clocks = <&rcc LPTIM2_K>;
|
|
|
+ clock-names = "mux";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ trigger@1 {
|
|
|
+ compatible = "st,stm32-lptimer-trigger";
|
|
|
+ reg = <1>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ counter {
|
|
|
+ compatible = "st,stm32-lptimer-counter";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ lptimer3: timer@50022000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32-lptimer";
|
|
|
+ reg = <0x50022000 0x400>;
|
|
|
+ clocks = <&rcc LPTIM3_K>;
|
|
|
+ clock-names = "mux";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ trigger@2 {
|
|
|
+ compatible = "st,stm32-lptimer-trigger";
|
|
|
+ reg = <2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ lptimer4: timer@50023000 {
|
|
|
+ compatible = "st,stm32-lptimer";
|
|
|
+ reg = <0x50023000 0x400>;
|
|
|
+ clocks = <&rcc LPTIM4_K>;
|
|
|
+ clock-names = "mux";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ lptimer5: timer@50024000 {
|
|
|
+ compatible = "st,stm32-lptimer";
|
|
|
+ reg = <0x50024000 0x400>;
|
|
|
+ clocks = <&rcc LPTIM5_K>;
|
|
|
+ clock-names = "mux";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ pwm {
|
|
|
+ compatible = "st,stm32-pwm-lp";
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ vrefbuf: vrefbuf@50025000 {
|
|
|
+ compatible = "st,stm32-vrefbuf";
|
|
|
+ reg = <0x50025000 0x8>;
|
|
|
+ regulator-min-microvolt = <1500000>;
|
|
|
+ regulator-max-microvolt = <2500000>;
|
|
|
+ clocks = <&rcc VREF>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ sai4: sai@50027000 {
|
|
|
+ compatible = "st,stm32h7-sai";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+ ranges = <0 0x50027000 0x400>;
|
|
|
+ reg = <0x50027000 0x4>;
|
|
|
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ resets = <&rcc SAI4_R>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ sai4a: audio-controller@50027004 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "st,stm32-sai-sub-a";
|
|
|
+ reg = <0x04 0x1c>;
|
|
|
+ clocks = <&rcc SAI4_K>;
|
|
|
+ clock-names = "sai_ck";
|
|
|
+ dmas = <&dmamux1 99 0x400 0x01>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ sai4b: audio-controller@50027024 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "st,stm32-sai-sub-b";
|
|
|
+ reg = <0x24 0x1c>;
|
|
|
+ clocks = <&rcc SAI4_K>;
|
|
|
+ clock-names = "sai_ck";
|
|
|
+ dmas = <&dmamux1 100 0x400 0x01>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ dts: thermal@50028000 {
|
|
|
+ compatible = "st,stm32-thermal";
|
|
|
+ reg = <0x50028000 0x100>;
|
|
|
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc TMPSENS>;
|
|
|
+ clock-names = "pclk";
|
|
|
+ #thermal-sensor-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ hdp: hdp@5002a000 {
|
|
|
+ compatible = "st,stm32mp1-hdp";
|
|
|
+ reg = <0x5002a000 0x400>;
|
|
|
+ clocks = <&rcc HDP>;
|
|
|
+ clock-names = "hdp";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ funnel: funnel@50091000 {
|
|
|
+ compatible = "arm,coresight-funnel", "arm,primecell";
|
|
|
+ reg = <0x50091000 0x1000>;
|
|
|
+ clocks = <&rcc CK_TRACE>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ /* funnel input ports */
|
|
|
+ port@0 {
|
|
|
+ reg = <0>;
|
|
|
+ funnel_in_port0: endpoint {
|
|
|
+ slave-mode;
|
|
|
+ remote-endpoint = <&stm_out_port>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ port@1 {
|
|
|
+ reg = <1>;
|
|
|
+ funnel_in_port1: endpoint {
|
|
|
+ slave-mode; /* A7-1 input */
|
|
|
+ remote-endpoint = <&etm1_out_port>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ port@2 {
|
|
|
+ reg = <2>;
|
|
|
+ funnel_in_port2: endpoint {
|
|
|
+ slave-mode; /* A7-2 input */
|
|
|
+ remote-endpoint = <&etm2_out_port>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ port@4 {
|
|
|
+ reg = <4>;
|
|
|
+ funnel_in_port4: endpoint {
|
|
|
+ slave-mode; /* REPLICATOR input */
|
|
|
+ remote-endpoint = <&replicator_out_port0>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ port@5 {
|
|
|
+ reg = <0>;
|
|
|
+ funnel_out_port0: endpoint {
|
|
|
+ remote-endpoint = <&etf_in_port>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ etf: etf@50092000 {
|
|
|
+ compatible = "arm,coresight-tmc", "arm,primecell";
|
|
|
+ reg = <0x50092000 0x1000>;
|
|
|
+ clocks = <&rcc CK_TRACE>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@0 {
|
|
|
+ reg = <0>;
|
|
|
+ etf_in_port: endpoint {
|
|
|
+ slave-mode;
|
|
|
+ remote-endpoint = <&funnel_out_port0>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ port@1 {
|
|
|
+ reg = <0>;
|
|
|
+ etf_out_port: endpoint {
|
|
|
+ remote-endpoint = <&tpiu_in_port>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ tpiu: tpiu@50093000 {
|
|
|
+ compatible = "arm,coresight-tpiu", "arm,primecell";
|
|
|
+ reg = <0x50093000 0x1000>;
|
|
|
+ clocks = <&rcc CK_TRACE>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+
|
|
|
+ port {
|
|
|
+ tpiu_in_port: endpoint {
|
|
|
+ slave-mode;
|
|
|
+ remote-endpoint = <&etf_out_port>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ stm: stm@500a0000 {
|
|
|
+ compatible = "arm,coresight-stm", "arm,primecell";
|
|
|
+ reg = <0x500a0000 0x1000>, <0x90000000 0x1000000>,
|
|
|
+ <0x50094000 0x1000>;
|
|
|
+ reg-names = "stm-base", "stm-stimulus-base", "cti-base";
|
|
|
+
|
|
|
+ clocks = <&rcc CK_TRACE>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@0 {
|
|
|
+ reg = <0>;
|
|
|
+ stm_out_port: endpoint {
|
|
|
+ remote-endpoint = <&funnel_in_port0>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ /* Cortex A7-1 */
|
|
|
+ etm1: etm@500dc000 {
|
|
|
+ compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
|
+ reg = <0x500dc000 0x1000>;
|
|
|
+ cpu = <&cpu0>;
|
|
|
+ clocks = <&rcc CK_TRACE>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+ port {
|
|
|
+ etm1_out_port: endpoint {
|
|
|
+ remote-endpoint = <&funnel_in_port1>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ /* Cortex A7-2 */
|
|
|
+ etm2: etm@500dd000 {
|
|
|
+ compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
|
+ reg = <0x500dd000 0x1000>;
|
|
|
+ cpu = <&cpu1>;
|
|
|
+ clocks = <&rcc CK_TRACE>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+
|
|
|
+ port {
|
|
|
+ etm2_out_port: endpoint {
|
|
|
+ remote-endpoint = <&funnel_in_port2>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ cryp1: cryp@54001000 {
|
|
|
+ compatible = "st,stm32mp1-cryp";
|
|
|
+ reg = <0x54001000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc CRYP1>;
|
|
|
+ resets = <&rcc CRYP1_R>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ hash1: hash@54002000 {
|
|
|
+ compatible = "st,stm32f756-hash";
|
|
|
+ reg = <0x54002000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc HASH1>;
|
|
|
+ resets = <&rcc HASH1_R>;
|
|
|
+ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>;
|
|
|
+ dma-names = "in";
|
|
|
+ dma-maxburst = <2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ rng1: rng@54003000 {
|
|
|
+ compatible = "st,stm32-rng";
|
|
|
+ reg = <0x54003000 0x400>;
|
|
|
+ clocks = <&rcc RNG1_K>;
|
|
|
+ resets = <&rcc RNG1_R>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ mdma1: dma@58000000 {
|
|
|
+ compatible = "st,stm32h7-mdma";
|
|
|
+ reg = <0x58000000 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc MDMA>;
|
|
|
+ resets = <&rcc MDMA_R>;
|
|
|
+ #dma-cells = <6>;
|
|
|
+ dma-channels = <32>;
|
|
|
+ dma-requests = <48>;
|
|
|
+ };
|
|
|
+
|
|
|
+ fmc: nand-controller@58002000 {
|
|
|
+ compatible = "st,stm32mp15-fmc2";
|
|
|
+ reg = <0x58002000 0x1000>,
|
|
|
+ <0x80000000 0x1000>,
|
|
|
+ <0x88010000 0x1000>,
|
|
|
+ <0x88020000 0x1000>,
|
|
|
+ <0x81000000 0x1000>,
|
|
|
+ <0x89010000 0x1000>,
|
|
|
+ <0x89020000 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&mdma1 20 0x2 0x12000A02 0x0 0x0 0>,
|
|
|
+ <&mdma1 20 0x2 0x12000A08 0x0 0x0 0>,
|
|
|
+ <&mdma1 21 0x2 0x12000A0A 0x0 0x0 0>;
|
|
|
+ dma-names = "tx", "rx", "ecc";
|
|
|
+ clocks = <&rcc FMC_K>;
|
|
|
+ resets = <&rcc FMC_R>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ qspi: spi@58003000 {
|
|
|
+ compatible = "st,stm32f469-qspi";
|
|
|
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
|
|
+ reg-names = "qspi", "qspi_mm";
|
|
|
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ dmas = <&mdma1 22 0x2 0x100002 0x0 0x0 0x0>,
|
|
|
+ <&mdma1 22 0x2 0x100008 0x0 0x0 0x0>;
|
|
|
+ dma-names = "tx", "rx";
|
|
|
+ clocks = <&rcc QSPI_K>;
|
|
|
+ resets = <&rcc QSPI_R>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ sdmmc1: sdmmc@58005000 {
|
|
|
+ compatible = "arm,pl18x", "arm,primecell";
|
|
|
+ arm,primecell-periphid = <0x00253180>;
|
|
|
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "cmd_irq";
|
|
|
+ clocks = <&rcc SDMMC1_K>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+ resets = <&rcc SDMMC1_R>;
|
|
|
+ cap-sd-highspeed;
|
|
|
+ cap-mmc-highspeed;
|
|
|
+ max-frequency = <120000000>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ sdmmc2: sdmmc@58007000 {
|
|
|
+ compatible = "arm,pl18x", "arm,primecell";
|
|
|
+ arm,primecell-periphid = <0x00253180>;
|
|
|
+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "cmd_irq";
|
|
|
+ clocks = <&rcc SDMMC2_K>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+ resets = <&rcc SDMMC2_R>;
|
|
|
+ cap-sd-highspeed;
|
|
|
+ cap-mmc-highspeed;
|
|
|
+ max-frequency = <120000000>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ crc1: crc@58009000 {
|
|
|
+ compatible = "st,stm32f7-crc";
|
|
|
+ reg = <0x58009000 0x400>;
|
|
|
+ clocks = <&rcc CRC1>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ stmmac_axi_config_0: stmmac-axi-config {
|
|
|
+ snps,wr_osr_lmt = <0x7>;
|
|
|
+ snps,rd_osr_lmt = <0x7>;
|
|
|
+ snps,blen = <0 0 0 0 16 8 4>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ethernet0: ethernet@5800a000 {
|
|
|
+ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
|
|
|
+ reg = <0x5800a000 0x2000>;
|
|
|
+ reg-names = "stmmaceth";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 70 1>;
|
|
|
+ interrupt-names = "macirq",
|
|
|
+ "eth_wake_irq",
|
|
|
+ "stm32_pwr_wakeup";
|
|
|
+ clock-names = "stmmaceth",
|
|
|
+ "mac-clk-tx",
|
|
|
+ "mac-clk-rx",
|
|
|
+ "eth-ck", //custom
|
|
|
+ "syscfg-clk", //custom
|
|
|
+ "ethstp";
|
|
|
+ clocks = <&rcc ETHMAC>,
|
|
|
+ <&rcc ETHTX>,
|
|
|
+ <&rcc ETHRX>,
|
|
|
+ <&rcc ETHCK_K>, //custom
|
|
|
+ <&rcc SYSCFG>, //custom
|
|
|
+ <&rcc ETHSTP>;
|
|
|
+ st,syscon = <&syscfg 0x4>;
|
|
|
+ snps,mixed-burst;
|
|
|
+ snps,pbl = <2>;
|
|
|
+ snps,en-tx-lpi-clockgating;
|
|
|
+ snps,axi-config = <&stmmac_axi_config_0>;
|
|
|
+ snps,tso;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ usbh_ohci: usbh-ohci@5800c000 {
|
|
|
+ compatible = "generic-ohci";
|
|
|
+ reg = <0x5800c000 0x1000>;
|
|
|
+ clocks = <&rcc USBH>;
|
|
|
+ resets = <&rcc USBH_R>;
|
|
|
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ usbh_ehci: usbh-ehci@5800d000 {
|
|
|
+ compatible = "generic-ehci";
|
|
|
+ reg = <0x5800d000 0x1000>;
|
|
|
+ clocks = <&rcc USBH>;
|
|
|
+ resets = <&rcc USBH_R>;
|
|
|
+ interrupts-extended = <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 43 1>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ companion = <&usbh_ohci>;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ wakeup-source;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ gpu: gpu@59000000 {
|
|
|
+ compatible = "vivante,gc";
|
|
|
+ reg = <0x59000000 0x800>;
|
|
|
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc GPU>, <&rcc GPU_K>;
|
|
|
+ clock-names = "bus" ,"core";
|
|
|
+ resets = <&rcc GPU_R>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ dsi: dsi@5a000000 {
|
|
|
+ compatible = "st,stm32-dsi";
|
|
|
+ reg = <0x5a000000 0x800>;
|
|
|
+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
|
|
+ clock-names = "pclk", "ref", "px_clk";
|
|
|
+ resets = <&rcc DSI_R>;
|
|
|
+ reset-names = "apb";
|
|
|
+ phy-dsi-supply = <®18>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ ltdc: display-controller@5a001000 {
|
|
|
+ compatible = "st,stm32-ltdc";
|
|
|
+ reg = <0x5a001000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc LTDC_PX>;
|
|
|
+ clock-names = "lcd";
|
|
|
+ resets = <&rcc LTDC_R>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ iwdg2: watchdog@5a002000 {
|
|
|
+ compatible = "st,stm32mp1-iwdg";
|
|
|
+ reg = <0x5a002000 0x400>;
|
|
|
+ clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
|
|
+ clock-names = "pclk", "lsi";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ usbphyc: usbphyc@5a006000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ #clock-cells = <0>;
|
|
|
+ compatible = "st,stm32mp1-usbphyc";
|
|
|
+ reg = <0x5a006000 0x1000>;
|
|
|
+ clocks = <&rcc USBPHY_K>;
|
|
|
+ resets = <&rcc USBPHY_R>;
|
|
|
+ vdda1v1-supply = <®11>;
|
|
|
+ vdda1v8-supply = <®18>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ usbphyc_port0: usb-phy@0 {
|
|
|
+ #phy-cells = <0>;
|
|
|
+ reg = <0>;
|
|
|
+ };
|
|
|
+
|
|
|
+ usbphyc_port1: usb-phy@1 {
|
|
|
+ #phy-cells = <1>;
|
|
|
+ reg = <1>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ ddrperfm: perf@5a007000 {
|
|
|
+ compatible = "st,stm32-ddr-pmu";
|
|
|
+ reg = <0x5a007000 0x400>;
|
|
|
+ clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>;
|
|
|
+ clock-names = "bus", "ddr";
|
|
|
+ resets = <&rcc DDRPERFM_R>;
|
|
|
+ status = "okay";
|
|
|
+ };
|
|
|
+
|
|
|
+ usart1: serial@5c000000 {
|
|
|
+ compatible = "st,stm32h7-uart";
|
|
|
+ reg = <0x5c000000 0x400>;
|
|
|
+ interrupt-names = "event", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 26 1>;
|
|
|
+ clocks = <&rcc USART1_K>;
|
|
|
+ resets = <&rcc USART1_R>;
|
|
|
+ wakeup-source;
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi6: spi@5c001000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "st,stm32h7-spi";
|
|
|
+ reg = <0x5c001000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&rcc SPI6_K>;
|
|
|
+ resets = <&rcc SPI6_R>;
|
|
|
+ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0x0>,
|
|
|
+ <&mdma1 35 0x0 0x40002 0x0 0x0 0x0>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c4: i2c@5c002000 {
|
|
|
+ compatible = "st,stm32f7-i2c";
|
|
|
+ reg = <0x5c002000 0x400>;
|
|
|
+ interrupt-names = "event", "error", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 24 1>;
|
|
|
+ clocks = <&rcc I2C4_K>;
|
|
|
+ resets = <&rcc I2C4_R>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>,
|
|
|
+ <&mdma1 37 0x0 0x40002 0x0 0x0 0>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
|
|
|
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x8>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ rtc: rtc@5c004000 {
|
|
|
+ compatible = "st,stm32mp1-rtc";
|
|
|
+ reg = <0x5c004000 0x400>;
|
|
|
+ clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
|
|
+ clock-names = "pclk", "rtc_ck";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 19 1>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ bsec: nvmem@5c005000 {
|
|
|
+ compatible = "st,stm32mp15-bsec";
|
|
|
+ reg = <0x5c005000 0x400>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+
|
|
|
+ part_number_otp: part_number_otp@4 {
|
|
|
+ reg = <0x4 0x1>;
|
|
|
+ };
|
|
|
+ ts_cal1: calib@5c {
|
|
|
+ reg = <0x5c 0x2>;
|
|
|
+ };
|
|
|
+ ts_cal2: calib@5e {
|
|
|
+ reg = <0x5e 0x2>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c6: i2c@5c009000 {
|
|
|
+ compatible = "st,stm32f7-i2c";
|
|
|
+ reg = <0x5c009000 0x400>;
|
|
|
+ interrupt-names = "event", "error", "wakeup";
|
|
|
+ interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <&exti 54 1>;
|
|
|
+ clocks = <&rcc I2C6_K>;
|
|
|
+ resets = <&rcc I2C6_R>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ dmas = <&mdma1 38 0x0 0x40008 0x0 0x0 0>,
|
|
|
+ <&mdma1 39 0x0 0x40002 0x0 0x0 0>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ power-domains = <&pd_core>;
|
|
|
+ st,syscfg-fmp = <&syscfg 0x4 0x20>;
|
|
|
+ st,syscfg-fmp-clr = <&syscfg 0x44 0x20>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ tamp: tamp@5c00a000 {
|
|
|
+ compatible = "simple-bus", "syscon", "simple-mfd";
|
|
|
+ reg = <0x5c00a000 0x400>;
|
|
|
+
|
|
|
+ reboot-mode {
|
|
|
+ compatible = "syscon-reboot-mode";
|
|
|
+ offset = <0x150>; /* reg20 */
|
|
|
+ mask = <0xff>;
|
|
|
+ mode-normal = <0>;
|
|
|
+ mode-fastboot = <0x1>;
|
|
|
+ mode-recovery = <0x2>;
|
|
|
+ mode-stm32cubeprogrammer = <0x3>;
|
|
|
+ mode-ums_mmc0 = <0x10>;
|
|
|
+ mode-ums_mmc1 = <0x11>;
|
|
|
+ mode-ums_mmc2 = <0x12>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ m4_rproc: m4@0 {
|
|
|
+ compatible = "st,stm32mp1-rproc";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+
|
|
|
+ ranges = <0x00000000 0x38000000 0x10000>,
|
|
|
+ <0x30000000 0x30000000 0x60000>,
|
|
|
+ <0x10000000 0x10000000 0x60000>;
|
|
|
+ resets = <&rcc MCU_R>;
|
|
|
+ reset-names = "mcu_rst";
|
|
|
+ st,syscfg-pdds = <&pwr 0x014 0x1>;
|
|
|
+ st,syscfg-holdboot = <&rcc 0x10C 0x1>;
|
|
|
+ st,syscfg-tz = <&rcc 0x000 0x1>;
|
|
|
+ st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ m4_system_resources {
|
|
|
+ compatible = "rproc-srm-core";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ firmware {
|
|
|
+ optee {
|
|
|
+ compatible = "linaro,optee-tz";
|
|
|
+ method = "smc";
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
Kory Maincent