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@@ -0,0 +1,1490 @@
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+Upstream patch for DFG implementation for MIPS
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+
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+Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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+
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+From c921d19863ccf66bdd0ffa5d38eaf05efab6b136 Mon Sep 17 00:00:00 2001
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+From: "commit-queue@webkit.org"
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+ <commit-queue@webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
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+Date: Mon, 18 Feb 2013 19:25:23 +0000
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+Subject: [PATCH] MIPS DFG implementation.
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+ https://bugs.webkit.org/show_bug.cgi?id=101328
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+
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+Patch by Balazs Kilvady <kilvadyb@homejinni.com> on 2013-02-18
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+Reviewed by Oliver Hunt.
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+
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+DFG implementation for MIPS.
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+
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+Source/JavaScriptCore:
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+
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+* assembler/MIPSAssembler.h:
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+(JSC::MIPSAssembler::MIPSAssembler):
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+(JSC::MIPSAssembler::sllv):
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+(JSC::MIPSAssembler::movd):
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+(MIPSAssembler):
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+(JSC::MIPSAssembler::negd):
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+(JSC::MIPSAssembler::labelForWatchpoint):
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+(JSC::MIPSAssembler::label):
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+(JSC::MIPSAssembler::vmov):
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+(JSC::MIPSAssembler::linkDirectJump):
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+(JSC::MIPSAssembler::maxJumpReplacementSize):
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+(JSC::MIPSAssembler::revertJumpToMove):
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+(JSC::MIPSAssembler::replaceWithJump):
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+* assembler/MacroAssembler.h:
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+(MacroAssembler):
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+(JSC::MacroAssembler::poke):
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+* assembler/MacroAssemblerMIPS.h:
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+(JSC::MacroAssemblerMIPS::add32):
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+(MacroAssemblerMIPS):
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+(JSC::MacroAssemblerMIPS::and32):
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+(JSC::MacroAssemblerMIPS::lshift32):
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+(JSC::MacroAssemblerMIPS::mul32):
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+(JSC::MacroAssemblerMIPS::or32):
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+(JSC::MacroAssemblerMIPS::rshift32):
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+(JSC::MacroAssemblerMIPS::urshift32):
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+(JSC::MacroAssemblerMIPS::sub32):
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+(JSC::MacroAssemblerMIPS::xor32):
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+(JSC::MacroAssemblerMIPS::store32):
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+(JSC::MacroAssemblerMIPS::jump):
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+(JSC::MacroAssemblerMIPS::branchAdd32):
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+(JSC::MacroAssemblerMIPS::branchMul32):
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+(JSC::MacroAssemblerMIPS::branchSub32):
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+(JSC::MacroAssemblerMIPS::branchNeg32):
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+(JSC::MacroAssemblerMIPS::call):
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+(JSC::MacroAssemblerMIPS::loadDouble):
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+(JSC::MacroAssemblerMIPS::moveDouble):
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+(JSC::MacroAssemblerMIPS::swapDouble):
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+(JSC::MacroAssemblerMIPS::subDouble):
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+(JSC::MacroAssemblerMIPS::mulDouble):
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+(JSC::MacroAssemblerMIPS::divDouble):
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+(JSC::MacroAssemblerMIPS::negateDouble):
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+(JSC::MacroAssemblerMIPS::branchEqual):
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+(JSC::MacroAssemblerMIPS::branchNotEqual):
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+(JSC::MacroAssemblerMIPS::branchTruncateDoubleToInt32):
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+(JSC::MacroAssemblerMIPS::branchTruncateDoubleToUint32):
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+(JSC::MacroAssemblerMIPS::truncateDoubleToInt32):
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+(JSC::MacroAssemblerMIPS::truncateDoubleToUint32):
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+(JSC::MacroAssemblerMIPS::branchDoubleNonZero):
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+(JSC::MacroAssemblerMIPS::branchDoubleZeroOrNaN):
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+(JSC::MacroAssemblerMIPS::invert):
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+(JSC::MacroAssemblerMIPS::replaceWithJump):
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+(JSC::MacroAssemblerMIPS::maxJumpReplacementSize):
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+* dfg/DFGAssemblyHelpers.h:
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+(AssemblyHelpers):
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+(JSC::DFG::AssemblyHelpers::preserveReturnAddressAfterCall):
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+(JSC::DFG::AssemblyHelpers::restoreReturnAddressBeforeReturn):
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+(JSC::DFG::AssemblyHelpers::debugCall):
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+* dfg/DFGCCallHelpers.h:
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+(CCallHelpers):
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+(JSC::DFG::CCallHelpers::setupArguments):
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+(JSC::DFG::CCallHelpers::setupArgumentsWithExecState):
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+* dfg/DFGFPRInfo.h:
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+(DFG):
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+(FPRInfo):
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+(JSC::DFG::FPRInfo::toRegister):
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+(JSC::DFG::FPRInfo::toIndex):
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+(JSC::DFG::FPRInfo::debugName):
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+* dfg/DFGGPRInfo.h:
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+(DFG):
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+(GPRInfo):
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+(JSC::DFG::GPRInfo::toRegister):
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+(JSC::DFG::GPRInfo::toIndex):
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+(JSC::DFG::GPRInfo::debugName):
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+* dfg/DFGSpeculativeJIT.h:
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+(SpeculativeJIT):
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+* jit/JSInterfaceJIT.h:
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+(JSInterfaceJIT):
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+* runtime/JSGlobalData.h:
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+(JSC::ScratchBuffer::allocationSize):
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+(ScratchBuffer):
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+
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+Source/WTF:
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+
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+* wtf/Platform.h:
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+
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+git-svn-id: http://svn.webkit.org/repository/webkit/trunk@143247 268f45cc-cd09-0410-ab3c-d52691b4dbfc
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+---
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+ Source/JavaScriptCore/ChangeLog | 90 ++++
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+ Source/JavaScriptCore/assembler/MIPSAssembler.h | 109 ++++-
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+ Source/JavaScriptCore/assembler/MacroAssembler.h | 7 +
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+ .../JavaScriptCore/assembler/MacroAssemblerMIPS.h | 480 +++++++++++++++++++--
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+ Source/JavaScriptCore/dfg/DFGAssemblyHelpers.h | 19 +-
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+ Source/JavaScriptCore/dfg/DFGCCallHelpers.h | 92 ++--
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+ Source/JavaScriptCore/dfg/DFGFPRInfo.h | 68 +++
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+ Source/JavaScriptCore/dfg/DFGGPRInfo.h | 67 +++
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+ Source/JavaScriptCore/dfg/DFGSpeculativeJIT.h | 4 +-
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+ Source/JavaScriptCore/jit/JSInterfaceJIT.h | 4 +
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+ Source/JavaScriptCore/runtime/JSGlobalData.h | 6 +-
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+ Source/WTF/ChangeLog | 11 +
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+ Source/WTF/wtf/Platform.h | 4 +
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+ 13 files changed, 888 insertions(+), 73 deletions(-)
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+
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+diff --git a/Source/JavaScriptCore/assembler/MIPSAssembler.h b/Source/JavaScriptCore/assembler/MIPSAssembler.h
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+index 026f87e..7f553bb 100644
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+--- a/Source/JavaScriptCore/assembler/MIPSAssembler.h
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++++ b/Source/JavaScriptCore/assembler/MIPSAssembler.h
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+@@ -152,6 +152,8 @@ public:
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+ typedef SegmentedVector<AssemblerLabel, 64> Jumps;
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+
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+ MIPSAssembler()
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++ : m_indexOfLastWatchpoint(INT_MIN)
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++ , m_indexOfTailOfLastWatchpoint(INT_MIN)
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+ {
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+ }
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+
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+@@ -325,7 +327,7 @@ public:
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+ emitInst(0x00000000 | (rd << OP_SH_RD) | (rt << OP_SH_RT) | ((shamt & 0x1f) << OP_SH_SHAMT));
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+ }
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+
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+- void sllv(RegisterID rd, RegisterID rt, int rs)
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++ void sllv(RegisterID rd, RegisterID rt, RegisterID rs)
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+ {
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+ emitInst(0x00000004 | (rd << OP_SH_RD) | (rt << OP_SH_RT) | (rs << OP_SH_RS));
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+ }
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+@@ -527,6 +529,16 @@ public:
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+ emitInst(0x46200004 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
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+ }
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+
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++ void movd(FPRegisterID fd, FPRegisterID fs)
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++ {
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++ emitInst(0x46200006 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
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++ }
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++
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++ void negd(FPRegisterID fd, FPRegisterID fs)
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++ {
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++ emitInst(0x46200007 | (fd << OP_SH_FD) | (fs << OP_SH_FS));
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++ }
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++
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+ void truncwd(FPRegisterID fd, FPRegisterID fs)
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+ {
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+ emitInst(0x4620000d | (fd << OP_SH_FD) | (fs << OP_SH_FS));
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+@@ -619,9 +631,24 @@ public:
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+ return m_buffer.label();
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+ }
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+
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++ AssemblerLabel labelForWatchpoint()
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++ {
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++ AssemblerLabel result = m_buffer.label();
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++ if (static_cast<int>(result.m_offset) != m_indexOfLastWatchpoint)
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++ result = label();
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++ m_indexOfLastWatchpoint = result.m_offset;
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++ m_indexOfTailOfLastWatchpoint = result.m_offset + maxJumpReplacementSize();
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++ return result;
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++ }
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++
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+ AssemblerLabel label()
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+ {
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+- return m_buffer.label();
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++ AssemblerLabel result = m_buffer.label();
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++ while (UNLIKELY(static_cast<int>(result.m_offset) < m_indexOfTailOfLastWatchpoint)) {
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++ nop();
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++ result = m_buffer.label();
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++ }
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++ return result;
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+ }
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+
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+ AssemblerLabel align(int alignment)
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+@@ -664,14 +691,24 @@ public:
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+ // Assembly helpers for moving data between fp and registers.
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+ void vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn)
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+ {
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++#if WTF_MIPS_ISA_REV(2) && WTF_MIPS_FP64
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++ mfc1(rd1, rn);
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++ mfhc1(rd2, rn);
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++#else
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+ mfc1(rd1, rn);
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+ mfc1(rd2, FPRegisterID(rn + 1));
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++#endif
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+ }
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+
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+ void vmov(FPRegisterID rd, RegisterID rn1, RegisterID rn2)
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+ {
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++#if WTF_MIPS_ISA_REV(2) && WTF_MIPS_FP64
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++ mtc1(rn1, rd);
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++ mthc1(rn2, rd);
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++#else
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+ mtc1(rn1, rd);
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+ mtc1(rn2, FPRegisterID(rd + 1));
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++#endif
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+ }
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+
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+ static unsigned getCallReturnOffset(AssemblerLabel call)
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+@@ -688,6 +725,35 @@ public:
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+ // writable region of memory; to modify the code in an execute-only execuable
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+ // pool the 'repatch' and 'relink' methods should be used.
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+
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++ static size_t linkDirectJump(void* code, void* to)
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++ {
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++ MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code));
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++ size_t ops = 0;
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++ int32_t slotAddr = reinterpret_cast<int>(insn) + 4;
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++ int32_t toAddr = reinterpret_cast<int>(to);
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++
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++ if ((slotAddr & 0xf0000000) != (toAddr & 0xf0000000)) {
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++ // lui
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++ *insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((toAddr >> 16) & 0xffff);
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++ ++insn;
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++ // ori
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++ *insn = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (toAddr & 0xffff);
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++ ++insn;
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++ // jr
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++ *insn = 0x00000008 | (MIPSRegisters::t9 << OP_SH_RS);
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++ ++insn;
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++ ops = 4 * sizeof(MIPSWord);
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++ } else {
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++ // j
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++ *insn = 0x08000000 | ((toAddr & 0x0fffffff) >> 2);
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++ ++insn;
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++ ops = 2 * sizeof(MIPSWord);
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++ }
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++ // nop
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++ *insn = 0x00000000;
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++ return ops;
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++ }
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++
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+ void linkJump(AssemblerLabel from, AssemblerLabel to)
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+ {
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+ ASSERT(to.isSet());
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+@@ -825,29 +891,36 @@ public:
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+ #endif
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+ }
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+
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+- static void revertJumpToMove(void* instructionStart, RegisterID rt, int imm)
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++ static ptrdiff_t maxJumpReplacementSize()
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+ {
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+- MIPSWord* insn = static_cast<MIPSWord*>(instructionStart) + 1;
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+- ASSERT((*insn & 0xfc000000) == 0x34000000);
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+- *insn = (*insn & 0xfc1f0000) | (imm & 0xffff);
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+- cacheFlush(insn, sizeof(MIPSWord));
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++ return sizeof(MIPSWord) * 4;
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+ }
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+
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+- static void replaceWithJump(void* instructionStart, void* to)
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++ static void revertJumpToMove(void* instructionStart, RegisterID rt, int imm)
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+ {
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+- MIPSWord* instruction = reinterpret_cast<MIPSWord*>(instructionStart);
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+- intptr_t jumpTo = reinterpret_cast<intptr_t>(to);
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++ MIPSWord* insn = static_cast<MIPSWord*>(instructionStart);
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++ size_t codeSize = 2 * sizeof(MIPSWord);
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+
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+ // lui
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+- instruction[0] = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((jumpTo >> 16) & 0xffff);
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++ *insn = 0x3c000000 | (rt << OP_SH_RT) | ((imm >> 16) & 0xffff);
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++ ++insn;
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+ // ori
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+- instruction[1] = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (jumpTo & 0xffff);
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+- // jr
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+- instruction[2] = 0x00000008 | (MIPSRegisters::t9 << OP_SH_RS);
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+- // nop
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+- instruction[3] = 0x0;
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++ *insn = 0x34000000 | (rt << OP_SH_RS) | (rt << OP_SH_RT) | (imm & 0xffff);
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++ ++insn;
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++ // if jr $t9
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++ if (*insn == 0x03200008) {
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++ *insn = 0x00000000;
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++ codeSize += sizeof(MIPSWord);
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++ }
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++ cacheFlush(insn, codeSize);
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++ }
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+
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+- cacheFlush(instruction, sizeof(MIPSWord) * 4);
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++ static void replaceWithJump(void* instructionStart, void* to)
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++ {
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++ ASSERT(!(bitwise_cast<uintptr_t>(instructionStart) & 3));
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++ ASSERT(!(bitwise_cast<uintptr_t>(to) & 3));
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++ size_t ops = linkDirectJump(instructionStart, to);
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++ cacheFlush(instructionStart, ops);
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+ }
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+
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+ static void replaceWithLoad(void* instructionStart)
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+@@ -1023,6 +1096,8 @@ private:
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+
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+ AssemblerBuffer m_buffer;
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+ Jumps m_jumps;
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++ int m_indexOfLastWatchpoint;
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++ int m_indexOfTailOfLastWatchpoint;
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+ };
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+
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+ } // namespace JSC
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+diff --git a/Source/JavaScriptCore/assembler/MacroAssembler.h b/Source/JavaScriptCore/assembler/MacroAssembler.h
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+index 60a93db..1f0c3de 100644
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+--- a/Source/JavaScriptCore/assembler/MacroAssembler.h
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++++ b/Source/JavaScriptCore/assembler/MacroAssembler.h
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+@@ -200,6 +200,13 @@ public:
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+ }
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+ #endif
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+
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++#if CPU(MIPS)
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++ void poke(FPRegisterID src, int index = 0)
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++ {
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++ ASSERT(!(index & 1));
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++ storeDouble(src, addressForPoke(index));
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++ }
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++#endif
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+
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+ // Backwards banches, these are currently all implemented using existing forwards branch mechanisms.
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+ void branchPtr(RelationalCondition cond, RegisterID op1, TrustedImmPtr imm, Label target)
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+diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h b/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h
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+index 43ad434..4f14960 100644
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+--- a/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h
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++++ b/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h
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+@@ -114,6 +114,11 @@ public:
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+ m_assembler.addu(dest, dest, src);
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+ }
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+
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++ void add32(RegisterID op1, RegisterID op2, RegisterID dest)
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++ {
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++ m_assembler.addu(dest, op1, op2);
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++ }
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++
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+ void add32(TrustedImm32 imm, RegisterID dest)
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+ {
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+ add32(imm, dest, dest);
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+@@ -267,6 +272,11 @@ public:
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+ m_assembler.andInsn(dest, dest, src);
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+ }
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+
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++ void and32(RegisterID op1, RegisterID op2, RegisterID dest)
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++ {
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++ m_assembler.andInsn(dest, op1, op2);
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++ }
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++
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+ void and32(TrustedImm32 imm, RegisterID dest)
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+ {
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+ if (!imm.m_value && !m_fixedWidth)
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+@@ -283,9 +293,16 @@ public:
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+ }
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+ }
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+
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+- void lshift32(TrustedImm32 imm, RegisterID dest)
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++ void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
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+ {
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+- m_assembler.sll(dest, dest, imm.m_value);
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++ if (!imm.m_value && !m_fixedWidth)
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++ move(MIPSRegisters::zero, dest);
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++ else if (imm.m_value > 0 && imm.m_value < 65535 && !m_fixedWidth)
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++ m_assembler.andi(dest, src, imm.m_value);
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++ else {
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++ move(imm, immTempRegister);
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++ m_assembler.andInsn(dest, src, immTempRegister);
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++ }
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+ }
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+
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+ void lshift32(RegisterID shiftAmount, RegisterID dest)
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+@@ -293,11 +310,33 @@ public:
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+ m_assembler.sllv(dest, dest, shiftAmount);
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+ }
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+
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++ void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
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++ {
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++ m_assembler.sllv(dest, src, shiftAmount);
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++ }
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++
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++ void lshift32(TrustedImm32 imm, RegisterID dest)
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++ {
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++ move(imm, immTempRegister);
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++ m_assembler.sllv(dest, dest, immTempRegister);
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++ }
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++
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++ void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
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++ {
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++ move(imm, immTempRegister);
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++ m_assembler.sllv(dest, src, immTempRegister);
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++ }
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++
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+ void mul32(RegisterID src, RegisterID dest)
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+ {
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+ m_assembler.mul(dest, dest, src);
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+ }
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+
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++ void mul32(RegisterID op1, RegisterID op2, RegisterID dest)
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++ {
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++ m_assembler.mul(dest, op1, op2);
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++ }
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++
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+ void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)
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+ {
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+ if (!imm.m_value && !m_fixedWidth)
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+@@ -348,6 +387,24 @@ public:
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+ m_assembler.orInsn(dest, dest, dataTempRegister);
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+ }
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+
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++ void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
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++ {
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++ if (!imm.m_value && !m_fixedWidth)
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++ return;
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++
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++ if (imm.m_value > 0 && imm.m_value < 65535 && !m_fixedWidth) {
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++ m_assembler.ori(dest, src, imm.m_value);
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++ return;
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++ }
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++
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++ /*
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++ li dataTemp, imm
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++ or dest, src, dataTemp
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++ */
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++ move(imm, dataTempRegister);
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++ m_assembler.orInsn(dest, src, dataTempRegister);
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++ }
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++
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+ void or32(RegisterID src, AbsoluteAddress dest)
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+ {
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+ load32(dest.m_ptr, dataTempRegister);
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+@@ -360,6 +417,11 @@ public:
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+ m_assembler.srav(dest, dest, shiftAmount);
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+ }
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+
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++ void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
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++ {
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++ m_assembler.srav(dest, src, shiftAmount);
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++ }
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++
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+ void rshift32(TrustedImm32 imm, RegisterID dest)
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+ {
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+ m_assembler.sra(dest, dest, imm.m_value);
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+@@ -375,16 +437,31 @@ public:
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+ m_assembler.srlv(dest, dest, shiftAmount);
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+ }
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+
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++ void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
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++ {
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++ m_assembler.srlv(dest, src, shiftAmount);
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|
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++ }
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++
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+ void urshift32(TrustedImm32 imm, RegisterID dest)
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|
|
+ {
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+ m_assembler.srl(dest, dest, imm.m_value);
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+ }
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+
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|
|
++ void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
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|
|
++ {
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|
|
++ m_assembler.srl(dest, src, imm.m_value);
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|
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++ }
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|
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++
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|
+ void sub32(RegisterID src, RegisterID dest)
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|
|
+ {
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|
+ m_assembler.subu(dest, dest, src);
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|
|
+ }
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|
|
+
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|
|
++ void sub32(RegisterID op1, RegisterID op2, RegisterID dest)
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|
|
++ {
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|
|
++ m_assembler.subu(dest, op1, op2);
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|
|
++ }
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++
|
|
|
+ void sub32(TrustedImm32 imm, RegisterID dest)
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|
|
+ {
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|
|
+ if (imm.m_value >= -32767 && imm.m_value <= 32768
|
|
|
+@@ -495,6 +572,11 @@ public:
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+ m_assembler.xorInsn(dest, dest, src);
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|
+ }
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+
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|
|
++ void xor32(RegisterID op1, RegisterID op2, RegisterID dest)
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|
|
++ {
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|
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++ m_assembler.xorInsn(dest, op1, op2);
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|
|
++ }
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|
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++
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|
|
+ void xor32(TrustedImm32 imm, RegisterID dest)
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|
|
+ {
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|
|
+ if (imm.m_value == -1) {
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|
|
+@@ -510,6 +592,21 @@ public:
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|
+ m_assembler.xorInsn(dest, dest, immTempRegister);
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|
|
+ }
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+
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|
|
++ void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)
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|
|
++ {
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|
|
++ if (imm.m_value == -1) {
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|
++ m_assembler.nor(dest, src, MIPSRegisters::zero);
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|
|
++ return;
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|
|
++ }
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|
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++
|
|
|
++ /*
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|
|
++ li immTemp, imm
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|
|
++ xor dest, dest, immTemp
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|
++ */
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|
++ move(imm, immTempRegister);
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|
++ m_assembler.xorInsn(dest, src, immTempRegister);
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|
|
++ }
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|
++
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|
|
+ void sqrtDouble(FPRegisterID src, FPRegisterID dst)
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|
|
+ {
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|
|
+ m_assembler.sqrtd(dst, src);
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|
|
+@@ -989,6 +1086,44 @@ public:
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|
|
+ }
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|
|
+ }
|
|
|
+
|
|
|
++ void store32(TrustedImm32 imm, BaseIndex address)
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|
|
++ {
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|
|
++ if (address.offset >= -32768 && address.offset <= 32767 && !m_fixedWidth) {
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|
|
++ /*
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|
|
++ sll addrTemp, address.index, address.scale
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|
|
++ addu addrTemp, addrTemp, address.base
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|
++ sw src, address.offset(addrTemp)
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|
|
++ */
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|
|
++ m_assembler.sll(addrTempRegister, address.index, address.scale);
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|
|
++ m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
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|
|
++ if (!imm.m_value)
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|
|
++ m_assembler.sw(MIPSRegisters::zero, addrTempRegister, address.offset);
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|
|
++ else {
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|
|
++ move(imm, immTempRegister);
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|
|
++ m_assembler.sw(immTempRegister, addrTempRegister, address.offset);
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|
|
++ }
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|
|
++ } else {
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|
|
++ /*
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|
|
++ sll addrTemp, address.index, address.scale
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|
|
++ addu addrTemp, addrTemp, address.base
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|
++ lui immTemp, (address.offset + 0x8000) >> 16
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|
|
++ addu addrTemp, addrTemp, immTemp
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|
|
++ sw src, (address.offset & 0xffff)(at)
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|
++ */
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|
++ m_assembler.sll(addrTempRegister, address.index, address.scale);
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|
++ m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
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|
|
++ m_assembler.lui(immTempRegister, (address.offset + 0x8000) >> 16);
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|
++ m_assembler.addu(addrTempRegister, addrTempRegister, immTempRegister);
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|
|
++ if (!imm.m_value && !m_fixedWidth)
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|
++ m_assembler.sw(MIPSRegisters::zero, addrTempRegister, address.offset);
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|
++ else {
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|
|
++ move(imm, immTempRegister);
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|
|
++ m_assembler.sw(immTempRegister, addrTempRegister, address.offset);
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|
|
++ }
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|
|
++ }
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|
|
++ }
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|
|
++
|
|
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++
|
|
|
+ void store32(RegisterID src, const void* address)
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|
|
+ {
|
|
|
+ /*
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|
|
+@@ -1336,6 +1471,15 @@ public:
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|
|
+ m_fixedWidth = false;
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|
|
+ }
|
|
|
+
|
|
|
++ void jump(AbsoluteAddress address)
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|
|
++ {
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|
|
++ m_fixedWidth = true;
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|
|
++ load32(address.m_ptr, MIPSRegisters::t9);
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|
|
++ m_assembler.jr(MIPSRegisters::t9);
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|
|
++ m_assembler.nop();
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|
|
++ m_fixedWidth = false;
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|
|
++ }
|
|
|
++
|
|
|
+ void moveDoubleToInts(FPRegisterID src, RegisterID dest1, RegisterID dest2)
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|
|
+ {
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|
|
+ m_assembler.vmov(dest1, dest2, src);
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|
|
+@@ -1404,6 +1548,53 @@ public:
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|
|
+ return Jump();
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|
|
+ }
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|
+
|
|
|
++ Jump branchAdd32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
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|
|
++ {
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|
|
++ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
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|
|
++ if (cond == Overflow) {
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|
|
++ /*
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|
|
++ move dataTemp, op1
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|
|
++ xor cmpTemp, dataTemp, op2
|
|
|
++ bltz cmpTemp, No_overflow # diff sign bit -> no overflow
|
|
|
++ addu dest, dataTemp, op2
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|
|
++ xor cmpTemp, dest, dataTemp
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|
|
++ bgez cmpTemp, No_overflow # same sign big -> no overflow
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|
|
++ nop
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|
|
++ b Overflow
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|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ No_overflow:
|
|
|
++ */
|
|
|
++ move(op1, dataTempRegister);
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|
|
++ m_assembler.xorInsn(cmpTempRegister, dataTempRegister, op2);
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|
|
++ m_assembler.bltz(cmpTempRegister, 10);
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|
|
++ m_assembler.addu(dest, dataTempRegister, op2);
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|
|
++ m_assembler.xorInsn(cmpTempRegister, dest, dataTempRegister);
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|
|
++ m_assembler.bgez(cmpTempRegister, 7);
|
|
|
++ m_assembler.nop();
|
|
|
++ return jump();
|
|
|
++ }
|
|
|
++ if (cond == Signed) {
|
|
|
++ add32(op1, op2, dest);
|
|
|
++ // Check if dest is negative.
|
|
|
++ m_assembler.slt(cmpTempRegister, dest, MIPSRegisters::zero);
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|
|
++ return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
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|
|
++ }
|
|
|
++ if (cond == Zero) {
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|
|
++ add32(op1, op2, dest);
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|
|
++ return branchEqual(dest, MIPSRegisters::zero);
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|
|
++ }
|
|
|
++ if (cond == NonZero) {
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|
|
++ add32(op1, op2, dest);
|
|
|
++ return branchNotEqual(dest, MIPSRegisters::zero);
|
|
|
++ }
|
|
|
++ ASSERT(0);
|
|
|
++ return Jump();
|
|
|
++ }
|
|
|
++
|
|
|
+ Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
|
|
|
+ {
|
|
|
+ move(imm, immTempRegister);
|
|
|
+@@ -1417,6 +1608,111 @@ public:
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|
|
+ return branchAdd32(cond, immTempRegister, dest);
|
|
|
+ }
|
|
|
+
|
|
|
++ Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, AbsoluteAddress dest)
|
|
|
++ {
|
|
|
++ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
|
++ if (cond == Overflow) {
|
|
|
++ /*
|
|
|
++ move dataTemp, dest
|
|
|
++ xori cmpTemp, dataTemp, imm
|
|
|
++ bltz cmpTemp, No_overflow # diff sign bit -> no overflow
|
|
|
++ addiu dataTemp, dataTemp, imm
|
|
|
++ move dest, dataTemp
|
|
|
++ xori cmpTemp, dataTemp, imm
|
|
|
++ bgez cmpTemp, No_overflow # same sign big -> no overflow
|
|
|
++ nop
|
|
|
++ b Overflow
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ No_overflow:
|
|
|
++ */
|
|
|
++ if (imm.m_value >= -32768 && imm.m_value <= 32767 && !m_fixedWidth) {
|
|
|
++ load32(dest.m_ptr, dataTempRegister);
|
|
|
++ m_assembler.xori(cmpTempRegister, dataTempRegister, imm.m_value);
|
|
|
++ m_assembler.bltz(cmpTempRegister, 10);
|
|
|
++ m_assembler.addiu(dataTempRegister, dataTempRegister, imm.m_value);
|
|
|
++ store32(dataTempRegister, dest.m_ptr);
|
|
|
++ m_assembler.xori(cmpTempRegister, dataTempRegister, imm.m_value);
|
|
|
++ m_assembler.bgez(cmpTempRegister, 7);
|
|
|
++ m_assembler.nop();
|
|
|
++ } else {
|
|
|
++ load32(dest.m_ptr, dataTempRegister);
|
|
|
++ move(imm, immTempRegister);
|
|
|
++ m_assembler.xorInsn(cmpTempRegister, dataTempRegister, immTempRegister);
|
|
|
++ m_assembler.bltz(cmpTempRegister, 10);
|
|
|
++ m_assembler.addiu(dataTempRegister, dataTempRegister, immTempRegister);
|
|
|
++ store32(dataTempRegister, dest.m_ptr);
|
|
|
++ m_assembler.xori(cmpTempRegister, dataTempRegister, immTempRegister);
|
|
|
++ m_assembler.bgez(cmpTempRegister, 7);
|
|
|
++ m_assembler.nop();
|
|
|
++ }
|
|
|
++ return jump();
|
|
|
++ }
|
|
|
++ move(imm, immTempRegister);
|
|
|
++ load32(dest.m_ptr, dataTempRegister);
|
|
|
++ add32(immTempRegister, dataTempRegister);
|
|
|
++ store32(dataTempRegister, dest.m_ptr);
|
|
|
++ if (cond == Signed) {
|
|
|
++ // Check if dest is negative.
|
|
|
++ m_assembler.slt(cmpTempRegister, dataTempRegister, MIPSRegisters::zero);
|
|
|
++ return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
|
|
|
++ }
|
|
|
++ if (cond == Zero)
|
|
|
++ return branchEqual(dataTempRegister, MIPSRegisters::zero);
|
|
|
++ if (cond == NonZero)
|
|
|
++ return branchNotEqual(dataTempRegister, MIPSRegisters::zero);
|
|
|
++ ASSERT(0);
|
|
|
++ return Jump();
|
|
|
++ }
|
|
|
++
|
|
|
++ Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
|
|
|
++ {
|
|
|
++ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
|
++ if (cond == Overflow) {
|
|
|
++ /*
|
|
|
++ mult src, dest
|
|
|
++ mfhi dataTemp
|
|
|
++ mflo dest
|
|
|
++ sra addrTemp, dest, 31
|
|
|
++ beq dataTemp, addrTemp, No_overflow # all sign bits (bit 63 to bit 31) are the same -> no overflow
|
|
|
++ nop
|
|
|
++ b Overflow
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ No_overflow:
|
|
|
++ */
|
|
|
++ m_assembler.mult(src1, src2);
|
|
|
++ m_assembler.mfhi(dataTempRegister);
|
|
|
++ m_assembler.mflo(dest);
|
|
|
++ m_assembler.sra(addrTempRegister, dest, 31);
|
|
|
++ m_assembler.beq(dataTempRegister, addrTempRegister, 7);
|
|
|
++ m_assembler.nop();
|
|
|
++ return jump();
|
|
|
++ }
|
|
|
++ if (cond == Signed) {
|
|
|
++ mul32(src1, src2, dest);
|
|
|
++ // Check if dest is negative.
|
|
|
++ m_assembler.slt(cmpTempRegister, dest, MIPSRegisters::zero);
|
|
|
++ return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
|
|
|
++ }
|
|
|
++ if (cond == Zero) {
|
|
|
++ mul32(src1, src2, dest);
|
|
|
++ return branchEqual(dest, MIPSRegisters::zero);
|
|
|
++ }
|
|
|
++ if (cond == NonZero) {
|
|
|
++ mul32(src1, src2, dest);
|
|
|
++ return branchNotEqual(dest, MIPSRegisters::zero);
|
|
|
++ }
|
|
|
++ ASSERT(0);
|
|
|
++ return Jump();
|
|
|
++ }
|
|
|
++
|
|
|
+ Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
|
|
|
+ {
|
|
|
+ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
|
+@@ -1465,8 +1761,7 @@ public:
|
|
|
+ Jump branchMul32(ResultCondition cond, TrustedImm32 imm, RegisterID src, RegisterID dest)
|
|
|
+ {
|
|
|
+ move(imm, immTempRegister);
|
|
|
+- move(src, dest);
|
|
|
+- return branchMul32(cond, immTempRegister, dest);
|
|
|
++ return branchMul32(cond, immTempRegister, src, dest);
|
|
|
+ }
|
|
|
+
|
|
|
+ Jump branchSub32(ResultCondition cond, RegisterID src, RegisterID dest)
|
|
|
+@@ -1525,8 +1820,60 @@ public:
|
|
|
+ Jump branchSub32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
|
|
|
+ {
|
|
|
+ move(imm, immTempRegister);
|
|
|
+- move(src, dest);
|
|
|
+- return branchSub32(cond, immTempRegister, dest);
|
|
|
++ return branchSub32(cond, src, immTempRegister, dest);
|
|
|
++ }
|
|
|
++
|
|
|
++ Jump branchSub32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
|
|
|
++ {
|
|
|
++ ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
|
|
|
++ if (cond == Overflow) {
|
|
|
++ /*
|
|
|
++ move dataTemp, op1
|
|
|
++ xor cmpTemp, dataTemp, op2
|
|
|
++ bgez cmpTemp, No_overflow # same sign bit -> no overflow
|
|
|
++ subu dest, dataTemp, op2
|
|
|
++ xor cmpTemp, dest, dataTemp
|
|
|
++ bgez cmpTemp, No_overflow # same sign bit -> no overflow
|
|
|
++ nop
|
|
|
++ b Overflow
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ nop
|
|
|
++ No_overflow:
|
|
|
++ */
|
|
|
++ move(op1, dataTempRegister);
|
|
|
++ m_assembler.xorInsn(cmpTempRegister, dataTempRegister, op2);
|
|
|
++ m_assembler.bgez(cmpTempRegister, 10);
|
|
|
++ m_assembler.subu(dest, dataTempRegister, op2);
|
|
|
++ m_assembler.xorInsn(cmpTempRegister, dest, dataTempRegister);
|
|
|
++ m_assembler.bgez(cmpTempRegister, 7);
|
|
|
++ m_assembler.nop();
|
|
|
++ return jump();
|
|
|
++ }
|
|
|
++ if (cond == Signed) {
|
|
|
++ sub32(op1, op2, dest);
|
|
|
++ // Check if dest is negative.
|
|
|
++ m_assembler.slt(cmpTempRegister, dest, MIPSRegisters::zero);
|
|
|
++ return branchNotEqual(cmpTempRegister, MIPSRegisters::zero);
|
|
|
++ }
|
|
|
++ if (cond == Zero) {
|
|
|
++ sub32(op1, op2, dest);
|
|
|
++ return branchEqual(dest, MIPSRegisters::zero);
|
|
|
++ }
|
|
|
++ if (cond == NonZero) {
|
|
|
++ sub32(op1, op2, dest);
|
|
|
++ return branchNotEqual(dest, MIPSRegisters::zero);
|
|
|
++ }
|
|
|
++ ASSERT(0);
|
|
|
++ return Jump();
|
|
|
++ }
|
|
|
++
|
|
|
++ Jump branchNeg32(ResultCondition cond, RegisterID srcDest)
|
|
|
++ {
|
|
|
++ m_assembler.li(dataTempRegister, -1);
|
|
|
++ return branchMul32(cond, dataTempRegister, srcDest);
|
|
|
+ }
|
|
|
+
|
|
|
+ Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)
|
|
|
+@@ -1578,7 +1925,8 @@ public:
|
|
|
+
|
|
|
+ Call call(RegisterID target)
|
|
|
+ {
|
|
|
+- m_assembler.jalr(target);
|
|
|
++ move(target, MIPSRegisters::t9);
|
|
|
++ m_assembler.jalr(MIPSRegisters::t9);
|
|
|
+ m_assembler.nop();
|
|
|
+ return Call(m_assembler.label(), Call::None);
|
|
|
+ }
|
|
|
+@@ -1822,7 +2170,7 @@ public:
|
|
|
+ lui immTemp, (address.offset + 0x8000) >> 16
|
|
|
+ addu addrTemp, addrTemp, immTemp
|
|
|
+ lwc1 dest, (address.offset & 0xffff)(at)
|
|
|
+- lwc1 dest+4, (address.offset & 0xffff + 4)(at)
|
|
|
++ lwc1 dest+1, (address.offset & 0xffff + 4)(at)
|
|
|
+ */
|
|
|
+ m_assembler.sll(addrTempRegister, address.index, address.scale);
|
|
|
+ m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
|
|
|
+@@ -2009,6 +2357,19 @@ public:
|
|
|
+ #endif
|
|
|
+ }
|
|
|
+
|
|
|
++ void moveDouble(FPRegisterID src, FPRegisterID dest)
|
|
|
++ {
|
|
|
++ if (src != dest || m_fixedWidth)
|
|
|
++ m_assembler.movd(dest, src);
|
|
|
++ }
|
|
|
++
|
|
|
++ void swapDouble(FPRegisterID fr1, FPRegisterID fr2)
|
|
|
++ {
|
|
|
++ moveDouble(fr1, fpTempRegister);
|
|
|
++ moveDouble(fr2, fr1);
|
|
|
++ moveDouble(fpTempRegister, fr2);
|
|
|
++ }
|
|
|
++
|
|
|
+ void addDouble(FPRegisterID src, FPRegisterID dest)
|
|
|
+ {
|
|
|
+ m_assembler.addd(dest, dest, src);
|
|
|
+@@ -2036,6 +2397,11 @@ public:
|
|
|
+ m_assembler.subd(dest, dest, src);
|
|
|
+ }
|
|
|
+
|
|
|
++ void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
|
|
|
++ {
|
|
|
++ m_assembler.subd(dest, op1, op2);
|
|
|
++ }
|
|
|
++
|
|
|
+ void subDouble(Address src, FPRegisterID dest)
|
|
|
+ {
|
|
|
+ loadDouble(src, fpTempRegister);
|
|
|
+@@ -2053,11 +2419,32 @@ public:
|
|
|
+ m_assembler.muld(dest, dest, fpTempRegister);
|
|
|
+ }
|
|
|
+
|
|
|
++ void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
|
|
|
++ {
|
|
|
++ m_assembler.muld(dest, op1, op2);
|
|
|
++ }
|
|
|
++
|
|
|
+ void divDouble(FPRegisterID src, FPRegisterID dest)
|
|
|
+ {
|
|
|
+ m_assembler.divd(dest, dest, src);
|
|
|
+ }
|
|
|
+
|
|
|
++ void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
|
|
|
++ {
|
|
|
++ m_assembler.divd(dest, op1, op2);
|
|
|
++ }
|
|
|
++
|
|
|
++ void divDouble(Address src, FPRegisterID dest)
|
|
|
++ {
|
|
|
++ loadDouble(src, fpTempRegister);
|
|
|
++ m_assembler.divd(dest, dest, fpTempRegister);
|
|
|
++ }
|
|
|
++
|
|
|
++ void negateDouble(FPRegisterID src, FPRegisterID dest)
|
|
|
++ {
|
|
|
++ m_assembler.negd(dest, src);
|
|
|
++ }
|
|
|
++
|
|
|
+ void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
|
|
|
+ {
|
|
|
+ m_assembler.mtc1(src, fpTempRegister);
|
|
|
+@@ -2117,6 +2504,8 @@ public:
|
|
|
+
|
|
|
+ Jump branchEqual(RegisterID rs, RegisterID rt)
|
|
|
+ {
|
|
|
++ m_assembler.nop();
|
|
|
++ m_assembler.nop();
|
|
|
+ m_assembler.appendJump();
|
|
|
+ m_assembler.beq(rs, rt, 0);
|
|
|
+ m_assembler.nop();
|
|
|
+@@ -2126,6 +2515,8 @@ public:
|
|
|
+
|
|
|
+ Jump branchNotEqual(RegisterID rs, RegisterID rt)
|
|
|
+ {
|
|
|
++ m_assembler.nop();
|
|
|
++ m_assembler.nop();
|
|
|
+ m_assembler.appendJump();
|
|
|
+ m_assembler.bne(rs, rt, 0);
|
|
|
+ m_assembler.nop();
|
|
|
+@@ -2192,11 +2583,33 @@ public:
|
|
|
+ // If the result is not representable as a 32 bit value, branch.
|
|
|
+ // May also branch for some values that are representable in 32 bits
|
|
|
+ // (specifically, in this case, INT_MAX 0x7fffffff).
|
|
|
+- Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)
|
|
|
++ enum BranchTruncateType { BranchIfTruncateFailed, BranchIfTruncateSuccessful };
|
|
|
++ Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
|
|
|
++ {
|
|
|
++ m_assembler.truncwd(fpTempRegister, src);
|
|
|
++ m_assembler.mfc1(dest, fpTempRegister);
|
|
|
++ return branch32(branchType == BranchIfTruncateFailed ? Equal : NotEqual, dest, TrustedImm32(0x7fffffff));
|
|
|
++ }
|
|
|
++
|
|
|
++ Jump branchTruncateDoubleToUint32(FPRegisterID src, RegisterID dest, BranchTruncateType branchType = BranchIfTruncateFailed)
|
|
|
++ {
|
|
|
++ m_assembler.truncwd(fpTempRegister, src);
|
|
|
++ m_assembler.mfc1(dest, fpTempRegister);
|
|
|
++ return branch32(branchType == BranchIfTruncateFailed ? Equal : NotEqual, dest, TrustedImm32(0));
|
|
|
++ }
|
|
|
++
|
|
|
++ // Result is undefined if the value is outside of the integer range.
|
|
|
++ void truncateDoubleToInt32(FPRegisterID src, RegisterID dest)
|
|
|
++ {
|
|
|
++ m_assembler.truncwd(fpTempRegister, src);
|
|
|
++ m_assembler.mfc1(dest, fpTempRegister);
|
|
|
++ }
|
|
|
++
|
|
|
++ // Result is undefined if src > 2^31
|
|
|
++ void truncateDoubleToUint32(FPRegisterID src, RegisterID dest)
|
|
|
+ {
|
|
|
+ m_assembler.truncwd(fpTempRegister, src);
|
|
|
+ m_assembler.mfc1(dest, fpTempRegister);
|
|
|
+- return branch32(Equal, dest, TrustedImm32(0x7fffffff));
|
|
|
+ }
|
|
|
+
|
|
|
+ // Convert 'src' to an integer, and places the resulting 'dest'.
|
|
|
+@@ -2218,28 +2631,43 @@ public:
|
|
|
+
|
|
|
+ Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch)
|
|
|
+ {
|
|
|
+-#if WTF_MIPS_ISA_REV(2) && WTF_MIPS_FP64
|
|
|
+- m_assembler.mtc1(MIPSRegisters::zero, scratch);
|
|
|
+- m_assembler.mthc1(MIPSRegisters::zero, scratch);
|
|
|
+-#else
|
|
|
+- m_assembler.mtc1(MIPSRegisters::zero, scratch);
|
|
|
+- m_assembler.mtc1(MIPSRegisters::zero, FPRegisterID(scratch + 1));
|
|
|
+-#endif
|
|
|
++ m_assembler.vmov(scratch, MIPSRegisters::zero, MIPSRegisters::zero);
|
|
|
+ return branchDouble(DoubleNotEqual, reg, scratch);
|
|
|
+ }
|
|
|
+
|
|
|
+ Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch)
|
|
|
+ {
|
|
|
+-#if WTF_MIPS_ISA_REV(2) && WTF_MIPS_FP64
|
|
|
+- m_assembler.mtc1(MIPSRegisters::zero, scratch);
|
|
|
+- m_assembler.mthc1(MIPSRegisters::zero, scratch);
|
|
|
+-#else
|
|
|
+- m_assembler.mtc1(MIPSRegisters::zero, scratch);
|
|
|
+- m_assembler.mtc1(MIPSRegisters::zero, FPRegisterID(scratch + 1));
|
|
|
+-#endif
|
|
|
++ m_assembler.vmov(scratch, MIPSRegisters::zero, MIPSRegisters::zero);
|
|
|
+ return branchDouble(DoubleEqualOrUnordered, reg, scratch);
|
|
|
+ }
|
|
|
+
|
|
|
++ // Invert a relational condition, e.g. == becomes !=, < becomes >=, etc.
|
|
|
++ static RelationalCondition invert(RelationalCondition cond)
|
|
|
++ {
|
|
|
++ RelationalCondition r;
|
|
|
++ if (cond == Equal)
|
|
|
++ r = NotEqual;
|
|
|
++ else if (cond == NotEqual)
|
|
|
++ r = Equal;
|
|
|
++ else if (cond == Above)
|
|
|
++ r = BelowOrEqual;
|
|
|
++ else if (cond == AboveOrEqual)
|
|
|
++ r = Below;
|
|
|
++ else if (cond == Below)
|
|
|
++ r = AboveOrEqual;
|
|
|
++ else if (cond == BelowOrEqual)
|
|
|
++ r = Above;
|
|
|
++ else if (cond == GreaterThan)
|
|
|
++ r = LessThanOrEqual;
|
|
|
++ else if (cond == GreaterThanOrEqual)
|
|
|
++ r = LessThan;
|
|
|
++ else if (cond == LessThan)
|
|
|
++ r = GreaterThanOrEqual;
|
|
|
++ else if (cond == LessThanOrEqual)
|
|
|
++ r = GreaterThan;
|
|
|
++ return r;
|
|
|
++ }
|
|
|
++
|
|
|
+ void nop()
|
|
|
+ {
|
|
|
+ m_assembler.nop();
|
|
|
+@@ -2252,12 +2680,12 @@ public:
|
|
|
+
|
|
|
+ static void replaceWithJump(CodeLocationLabel instructionStart, CodeLocationLabel destination)
|
|
|
+ {
|
|
|
+- RELEASE_ASSERT_NOT_REACHED();
|
|
|
++ MIPSAssembler::replaceWithJump(instructionStart.dataLocation(), destination.dataLocation());
|
|
|
+ }
|
|
|
+
|
|
|
+ static ptrdiff_t maxJumpReplacementSize()
|
|
|
+ {
|
|
|
+- RELEASE_ASSERT_NOT_REACHED();
|
|
|
++ MIPSAssembler::maxJumpReplacementSize();
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+diff --git a/Source/JavaScriptCore/dfg/DFGAssemblyHelpers.h b/Source/JavaScriptCore/dfg/DFGAssemblyHelpers.h
|
|
|
+index fa0f5e0..573d8dc 100644
|
|
|
+--- a/Source/JavaScriptCore/dfg/DFGAssemblyHelpers.h
|
|
|
++++ b/Source/JavaScriptCore/dfg/DFGAssemblyHelpers.h
|
|
|
+@@ -93,6 +93,23 @@ public:
|
|
|
+ }
|
|
|
+ #endif
|
|
|
+
|
|
|
++#if CPU(MIPS)
|
|
|
++ ALWAYS_INLINE void preserveReturnAddressAfterCall(RegisterID reg)
|
|
|
++ {
|
|
|
++ move(returnAddressRegister, reg);
|
|
|
++ }
|
|
|
++
|
|
|
++ ALWAYS_INLINE void restoreReturnAddressBeforeReturn(RegisterID reg)
|
|
|
++ {
|
|
|
++ move(reg, returnAddressRegister);
|
|
|
++ }
|
|
|
++
|
|
|
++ ALWAYS_INLINE void restoreReturnAddressBeforeReturn(Address address)
|
|
|
++ {
|
|
|
++ loadPtr(address, returnAddressRegister);
|
|
|
++ }
|
|
|
++#endif
|
|
|
++
|
|
|
+ void emitGetFromCallFrameHeaderPtr(JSStack::CallFrameHeaderEntry entry, GPRReg to)
|
|
|
+ {
|
|
|
+ loadPtr(Address(GPRInfo::callFrameRegister, entry * sizeof(Register)), to);
|
|
|
+@@ -193,7 +210,7 @@ public:
|
|
|
+ move(TrustedImmPtr(scratchBuffer->activeLengthPtr()), GPRInfo::regT0);
|
|
|
+ storePtr(TrustedImmPtr(scratchSize), GPRInfo::regT0);
|
|
|
+
|
|
|
+-#if CPU(X86_64) || CPU(ARM)
|
|
|
++#if CPU(X86_64) || CPU(ARM) || CPU(MIPS)
|
|
|
+ move(TrustedImmPtr(buffer), GPRInfo::argumentGPR2);
|
|
|
+ move(TrustedImmPtr(argument), GPRInfo::argumentGPR1);
|
|
|
+ move(GPRInfo::callFrameRegister, GPRInfo::argumentGPR0);
|
|
|
+diff --git a/Source/JavaScriptCore/dfg/DFGCCallHelpers.h b/Source/JavaScriptCore/dfg/DFGCCallHelpers.h
|
|
|
+index 8adde05..3d99f6f 100644
|
|
|
+--- a/Source/JavaScriptCore/dfg/DFGCCallHelpers.h
|
|
|
++++ b/Source/JavaScriptCore/dfg/DFGCCallHelpers.h
|
|
|
+@@ -576,6 +576,39 @@ public:
|
|
|
+ poke(GPRInfo::nonArgGPR0);
|
|
|
+ }
|
|
|
+ #endif // CPU(ARM_HARDFP)
|
|
|
++#elif CPU(MIPS)
|
|
|
++ ALWAYS_INLINE void setupArguments(FPRReg arg1)
|
|
|
++ {
|
|
|
++ moveDouble(arg1, FPRInfo::argumentFPR0);
|
|
|
++ }
|
|
|
++
|
|
|
++ ALWAYS_INLINE void setupArguments(FPRReg arg1, FPRReg arg2)
|
|
|
++ {
|
|
|
++ if (arg2 != FPRInfo::argumentFPR0) {
|
|
|
++ moveDouble(arg1, FPRInfo::argumentFPR0);
|
|
|
++ moveDouble(arg2, FPRInfo::argumentFPR1);
|
|
|
++ } else if (arg1 != FPRInfo::argumentFPR1) {
|
|
|
++ moveDouble(arg2, FPRInfo::argumentFPR1);
|
|
|
++ moveDouble(arg1, FPRInfo::argumentFPR0);
|
|
|
++ } else {
|
|
|
++ // Swap arg1, arg2.
|
|
|
++ swapDouble(FPRInfo::argumentFPR0, FPRInfo::argumentFPR1);
|
|
|
++ }
|
|
|
++ }
|
|
|
++
|
|
|
++ ALWAYS_INLINE void setupArgumentsWithExecState(FPRReg arg1, GPRReg arg2)
|
|
|
++ {
|
|
|
++ assembler().vmov(GPRInfo::argumentGPR2, GPRInfo::argumentGPR3, arg1);
|
|
|
++ move(GPRInfo::callFrameRegister, GPRInfo::argumentGPR0);
|
|
|
++ poke(arg2, 4);
|
|
|
++ }
|
|
|
++
|
|
|
++ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, GPRReg arg2, FPRReg arg3)
|
|
|
++ {
|
|
|
++ setupStubArguments(arg1, arg2);
|
|
|
++ move(GPRInfo::callFrameRegister, GPRInfo::argumentGPR0);
|
|
|
++ poke(arg3, 4);
|
|
|
++ }
|
|
|
+ #else
|
|
|
+ #error "DFG JIT not supported on this platform."
|
|
|
+ #endif
|
|
|
+@@ -803,119 +836,126 @@ public:
|
|
|
+ // These methods are suitable for any calling convention that provides for
|
|
|
+ // exactly 4 argument registers, e.g. ARMv7.
|
|
|
+ #if NUMBER_OF_ARGUMENT_REGISTERS == 4
|
|
|
++
|
|
|
++#if CPU(MIPS)
|
|
|
++#define POKE_ARGUMENT_OFFSET 4
|
|
|
++#else
|
|
|
++#define POKE_ARGUMENT_OFFSET 0
|
|
|
++#endif
|
|
|
++
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, GPRReg arg2, GPRReg arg3, GPRReg arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, GPRReg arg2, GPRReg arg3, TrustedImm32 arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, TrustedImmPtr arg2, TrustedImm32 arg3, GPRReg arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, TrustedImmPtr arg2, TrustedImm32 arg3, GPRReg arg4, GPRReg arg5)
|
|
|
+ {
|
|
|
+- poke(arg5, 1);
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg5, POKE_ARGUMENT_OFFSET + 1);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, GPRReg arg2, TrustedImm32 arg3, TrustedImm32 arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(TrustedImm32 arg1, TrustedImm32 arg2, GPRReg arg3, GPRReg arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, GPRReg arg2, GPRReg arg3, TrustedImmPtr arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, GPRReg arg2, GPRReg arg3, GPRReg arg4, GPRReg arg5)
|
|
|
+ {
|
|
|
+- poke(arg5, 1);
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg5, POKE_ARGUMENT_OFFSET + 1);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(TrustedImm32 arg1, GPRReg arg2, GPRReg arg3, GPRReg arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(TrustedImm32 arg1, GPRReg arg2, GPRReg arg3, TrustedImmPtr arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(TrustedImm32 arg1, GPRReg arg2, TrustedImm32 arg3, TrustedImmPtr arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(TrustedImm32 arg1, GPRReg arg2, TrustedImm32 arg3, GPRReg arg4)
|
|
|
+ {
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, GPRReg arg2, TrustedImm32 arg3, GPRReg arg4, GPRReg arg5)
|
|
|
+ {
|
|
|
+- poke(arg5, 1);
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg5, POKE_ARGUMENT_OFFSET + 1);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(GPRReg arg1, GPRReg arg2, TrustedImm32 arg3, GPRReg arg4, TrustedImm32 arg5)
|
|
|
+ {
|
|
|
+- poke(arg5, 1);
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg5, POKE_ARGUMENT_OFFSET + 1);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(TrustedImm32 arg1, GPRReg arg2, GPRReg arg3, GPRReg arg4, TrustedImmPtr arg5)
|
|
|
+ {
|
|
|
+- poke(arg5, 1);
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg5, POKE_ARGUMENT_OFFSET + 1);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(TrustedImm32 arg1, GPRReg arg2, GPRReg arg3, TrustedImm32 arg4, TrustedImm32 arg5)
|
|
|
+ {
|
|
|
+- poke(arg5, 1);
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg5, POKE_ARGUMENT_OFFSET + 1);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(TrustedImm32 arg1, TrustedImm32 arg2, TrustedImm32 arg3, GPRReg arg4, GPRReg arg5)
|
|
|
+ {
|
|
|
+- poke(arg5, 1);
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg5, POKE_ARGUMENT_OFFSET + 1);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+ ALWAYS_INLINE void setupArgumentsWithExecState(TrustedImm32 arg1, GPRReg arg2, GPRReg arg3, GPRReg arg4, GPRReg arg5)
|
|
|
+ {
|
|
|
+- poke(arg5, 1);
|
|
|
+- poke(arg4);
|
|
|
++ poke(arg5, POKE_ARGUMENT_OFFSET + 1);
|
|
|
++ poke(arg4, POKE_ARGUMENT_OFFSET);
|
|
|
+ setupArgumentsWithExecState(arg1, arg2, arg3);
|
|
|
+ }
|
|
|
+
|
|
|
+diff --git a/Source/JavaScriptCore/dfg/DFGFPRInfo.h b/Source/JavaScriptCore/dfg/DFGFPRInfo.h
|
|
|
+index 17aaa7d..e18ec06 100644
|
|
|
+--- a/Source/JavaScriptCore/dfg/DFGFPRInfo.h
|
|
|
++++ b/Source/JavaScriptCore/dfg/DFGFPRInfo.h
|
|
|
+@@ -164,6 +164,74 @@ public:
|
|
|
+
|
|
|
+ #endif
|
|
|
+
|
|
|
++#if CPU(MIPS)
|
|
|
++
|
|
|
++class FPRInfo {
|
|
|
++public:
|
|
|
++ typedef FPRReg RegisterType;
|
|
|
++ static const unsigned numberOfRegisters = 6;
|
|
|
++
|
|
|
++ // Temporary registers.
|
|
|
++ static const FPRReg fpRegT0 = MIPSRegisters::f0;
|
|
|
++ static const FPRReg fpRegT1 = MIPSRegisters::f4;
|
|
|
++ static const FPRReg fpRegT2 = MIPSRegisters::f6;
|
|
|
++ static const FPRReg fpRegT3 = MIPSRegisters::f8;
|
|
|
++ static const FPRReg fpRegT4 = MIPSRegisters::f10;
|
|
|
++ static const FPRReg fpRegT5 = MIPSRegisters::f18;
|
|
|
++
|
|
|
++ static const FPRReg returnValueFPR = MIPSRegisters::f0;
|
|
|
++
|
|
|
++ static const FPRReg argumentFPR0 = MIPSRegisters::f12;
|
|
|
++ static const FPRReg argumentFPR1 = MIPSRegisters::f14;
|
|
|
++
|
|
|
++ static FPRReg toRegister(unsigned index)
|
|
|
++ {
|
|
|
++ static const FPRReg registerForIndex[numberOfRegisters] = {
|
|
|
++ fpRegT0, fpRegT1, fpRegT2, fpRegT3, fpRegT4, fpRegT5 };
|
|
|
++
|
|
|
++ ASSERT(index < numberOfRegisters);
|
|
|
++ return registerForIndex[index];
|
|
|
++ }
|
|
|
++
|
|
|
++ static unsigned toIndex(FPRReg reg)
|
|
|
++ {
|
|
|
++ ASSERT(reg != InvalidFPRReg);
|
|
|
++ ASSERT(reg < 20);
|
|
|
++ static const unsigned indexForRegister[20] = {
|
|
|
++ 0, InvalidIndex, InvalidIndex, InvalidIndex,
|
|
|
++ 1, InvalidIndex, 2, InvalidIndex,
|
|
|
++ 3, InvalidIndex, 4, InvalidIndex,
|
|
|
++ InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex,
|
|
|
++ InvalidIndex, InvalidIndex, 5, InvalidIndex,
|
|
|
++ };
|
|
|
++ unsigned result = indexForRegister[reg];
|
|
|
++ ASSERT(result != InvalidIndex);
|
|
|
++ return result;
|
|
|
++ }
|
|
|
++
|
|
|
++ static const char* debugName(FPRReg reg)
|
|
|
++ {
|
|
|
++ ASSERT(reg != InvalidFPRReg);
|
|
|
++ ASSERT(reg < 32);
|
|
|
++ static const char* nameForRegister[32] = {
|
|
|
++ "f0", "f1", "f2", "f3",
|
|
|
++ "f4", "f5", "f6", "f7",
|
|
|
++ "f8", "f9", "f10", "f11",
|
|
|
++ "f12", "f13", "f14", "f15"
|
|
|
++ "f16", "f17", "f18", "f19"
|
|
|
++ "f20", "f21", "f22", "f23"
|
|
|
++ "f24", "f25", "f26", "f27"
|
|
|
++ "f28", "f29", "f30", "f31"
|
|
|
++ };
|
|
|
++ return nameForRegister[reg];
|
|
|
++ }
|
|
|
++private:
|
|
|
++
|
|
|
++ static const unsigned InvalidIndex = 0xffffffff;
|
|
|
++};
|
|
|
++
|
|
|
++#endif
|
|
|
++
|
|
|
+ typedef RegisterBank<FPRInfo>::iterator fpr_iterator;
|
|
|
+
|
|
|
+ } } // namespace JSC::DFG
|
|
|
+diff --git a/Source/JavaScriptCore/dfg/DFGGPRInfo.h b/Source/JavaScriptCore/dfg/DFGGPRInfo.h
|
|
|
+index 3d07556..aa634cd 100644
|
|
|
+--- a/Source/JavaScriptCore/dfg/DFGGPRInfo.h
|
|
|
++++ b/Source/JavaScriptCore/dfg/DFGGPRInfo.h
|
|
|
+@@ -461,6 +461,73 @@ private:
|
|
|
+
|
|
|
+ #endif
|
|
|
+
|
|
|
++#if CPU(MIPS)
|
|
|
++#define NUMBER_OF_ARGUMENT_REGISTERS 4
|
|
|
++
|
|
|
++class GPRInfo {
|
|
|
++public:
|
|
|
++ typedef GPRReg RegisterType;
|
|
|
++ static const unsigned numberOfRegisters = 6;
|
|
|
++
|
|
|
++ // Temporary registers.
|
|
|
++ static const GPRReg regT0 = MIPSRegisters::v0;
|
|
|
++ static const GPRReg regT1 = MIPSRegisters::v1;
|
|
|
++ static const GPRReg regT2 = MIPSRegisters::t4;
|
|
|
++ static const GPRReg regT3 = MIPSRegisters::t5;
|
|
|
++ static const GPRReg regT4 = MIPSRegisters::t6;
|
|
|
++ static const GPRReg regT5 = MIPSRegisters::t7;
|
|
|
++ // These registers match the baseline JIT.
|
|
|
++ static const GPRReg cachedResultRegister = regT0;
|
|
|
++ static const GPRReg cachedResultRegister2 = regT1;
|
|
|
++ static const GPRReg callFrameRegister = MIPSRegisters::s0;
|
|
|
++ // These constants provide the names for the general purpose argument & return value registers.
|
|
|
++ static const GPRReg argumentGPR0 = MIPSRegisters::a0;
|
|
|
++ static const GPRReg argumentGPR1 = MIPSRegisters::a1;
|
|
|
++ static const GPRReg argumentGPR2 = MIPSRegisters::a2;
|
|
|
++ static const GPRReg argumentGPR3 = MIPSRegisters::a3;
|
|
|
++ static const GPRReg nonArgGPR0 = regT2;
|
|
|
++ static const GPRReg nonArgGPR1 = regT3;
|
|
|
++ static const GPRReg nonArgGPR2 = regT4;
|
|
|
++ static const GPRReg returnValueGPR = regT0;
|
|
|
++ static const GPRReg returnValueGPR2 = regT1;
|
|
|
++ static const GPRReg nonPreservedNonReturnGPR = regT5;
|
|
|
++
|
|
|
++ static GPRReg toRegister(unsigned index)
|
|
|
++ {
|
|
|
++ ASSERT(index < numberOfRegisters);
|
|
|
++ static const GPRReg registerForIndex[numberOfRegisters] = { regT0, regT1, regT2, regT3, regT4, regT5 };
|
|
|
++ return registerForIndex[index];
|
|
|
++ }
|
|
|
++
|
|
|
++ static unsigned toIndex(GPRReg reg)
|
|
|
++ {
|
|
|
++ ASSERT(reg != InvalidGPRReg);
|
|
|
++ ASSERT(reg < 16);
|
|
|
++ static const unsigned indexForRegister[16] = { InvalidIndex, InvalidIndex, 0, 1, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, InvalidIndex, 2, 3, 4, 5 };
|
|
|
++ unsigned result = indexForRegister[reg];
|
|
|
++ ASSERT(result != InvalidIndex);
|
|
|
++ return result;
|
|
|
++ }
|
|
|
++
|
|
|
++ static const char* debugName(GPRReg reg)
|
|
|
++ {
|
|
|
++ ASSERT(reg != InvalidGPRReg);
|
|
|
++ ASSERT(reg < 16);
|
|
|
++ static const char* nameForRegister[16] = {
|
|
|
++ "zero", "at", "v0", "v1",
|
|
|
++ "a0", "a1", "a2", "a3",
|
|
|
++ "t0", "t1", "t2", "t3",
|
|
|
++ "t4", "t5", "t6", "t7"
|
|
|
++ };
|
|
|
++ return nameForRegister[reg];
|
|
|
++ }
|
|
|
++private:
|
|
|
++
|
|
|
++ static const unsigned InvalidIndex = 0xffffffff;
|
|
|
++};
|
|
|
++
|
|
|
++#endif
|
|
|
++
|
|
|
+ typedef RegisterBank<GPRInfo>::iterator gpr_iterator;
|
|
|
+
|
|
|
+ } } // namespace JSC::DFG
|
|
|
+diff --git a/Source/JavaScriptCore/dfg/DFGSpeculativeJIT.h b/Source/JavaScriptCore/dfg/DFGSpeculativeJIT.h
|
|
|
+index ea33f38..247274b 100644
|
|
|
+--- a/Source/JavaScriptCore/dfg/DFGSpeculativeJIT.h
|
|
|
++++ b/Source/JavaScriptCore/dfg/DFGSpeculativeJIT.h
|
|
|
+@@ -1241,7 +1241,7 @@ public:
|
|
|
+
|
|
|
+ // EncodedJSValue in JSVALUE32_64 is a 64-bit integer. When being compiled in ARM EABI, it must be aligned even-numbered register (r0, r2 or [sp]).
|
|
|
+ // To avoid assemblies from using wrong registers, let's occupy r1 or r3 with a dummy argument when necessary.
|
|
|
+-#if COMPILER_SUPPORTS(EABI) && CPU(ARM)
|
|
|
++#if (COMPILER_SUPPORTS(EABI) && CPU(ARM)) || CPU(MIPS)
|
|
|
+ #define EABI_32BIT_DUMMY_ARG TrustedImm32(0),
|
|
|
+ #else
|
|
|
+ #define EABI_32BIT_DUMMY_ARG
|
|
|
+@@ -1691,7 +1691,7 @@ public:
|
|
|
+ }
|
|
|
+ #endif
|
|
|
+
|
|
|
+-#if !defined(NDEBUG) && !CPU(ARM)
|
|
|
++#if !defined(NDEBUG) && !CPU(ARM) && !CPU(MIPS)
|
|
|
+ void prepareForExternalCall()
|
|
|
+ {
|
|
|
+ // We're about to call out to a "native" helper function. The helper
|
|
|
+diff --git a/Source/JavaScriptCore/jit/JSInterfaceJIT.h b/Source/JavaScriptCore/jit/JSInterfaceJIT.h
|
|
|
+index 7fdeaf0..48ad6b2 100644
|
|
|
+--- a/Source/JavaScriptCore/jit/JSInterfaceJIT.h
|
|
|
++++ b/Source/JavaScriptCore/jit/JSInterfaceJIT.h
|
|
|
+@@ -125,6 +125,10 @@ namespace JSC {
|
|
|
+ static const RegisterID cachedResultRegister = MIPSRegisters::v0;
|
|
|
+ static const RegisterID firstArgumentRegister = MIPSRegisters::a0;
|
|
|
+
|
|
|
++#if ENABLE(VALUE_PROFILER)
|
|
|
++ static const RegisterID bucketCounterRegister = MIPSRegisters::s3;
|
|
|
++#endif
|
|
|
++
|
|
|
+ // regT0 must be v0 for returning a 32-bit value.
|
|
|
+ static const RegisterID regT0 = MIPSRegisters::v0;
|
|
|
+
|
|
|
+diff --git a/Source/JavaScriptCore/runtime/JSGlobalData.h b/Source/JavaScriptCore/runtime/JSGlobalData.h
|
|
|
+index 5d47ab9..c02f336 100644
|
|
|
+--- a/Source/JavaScriptCore/runtime/JSGlobalData.h
|
|
|
++++ b/Source/JavaScriptCore/runtime/JSGlobalData.h
|
|
|
+@@ -141,14 +141,18 @@ namespace JSC {
|
|
|
+ return result;
|
|
|
+ }
|
|
|
+
|
|
|
+- static size_t allocationSize(size_t bufferSize) { return sizeof(size_t) + bufferSize; }
|
|
|
++ static size_t allocationSize(size_t bufferSize) { return sizeof(ScratchBuffer) + bufferSize; }
|
|
|
+ void setActiveLength(size_t activeLength) { m_activeLength = activeLength; }
|
|
|
+ size_t activeLength() const { return m_activeLength; };
|
|
|
+ size_t* activeLengthPtr() { return &m_activeLength; };
|
|
|
+ void* dataBuffer() { return m_buffer; }
|
|
|
+
|
|
|
+ size_t m_activeLength;
|
|
|
++#if CPU(MIPS) && (defined WTF_MIPS_ARCH_REV && WTF_MIPS_ARCH_REV == 2)
|
|
|
++ void* m_buffer[0] __attribute__((aligned(8)));
|
|
|
++#else
|
|
|
+ void* m_buffer[0];
|
|
|
++#endif
|
|
|
+ };
|
|
|
+ #if COMPILER(MSVC)
|
|
|
+ #pragma warning(pop)
|
|
|
+diff --git a/Source/WTF/wtf/Platform.h b/Source/WTF/wtf/Platform.h
|
|
|
+index 1698247..2d90359 100644
|
|
|
+--- a/Source/WTF/wtf/Platform.h
|
|
|
++++ b/Source/WTF/wtf/Platform.h
|
|
|
+@@ -818,6 +818,10 @@
|
|
|
+ #if CPU(ARM_TRADITIONAL)
|
|
|
+ #define ENABLE_DFG_JIT 1
|
|
|
+ #endif
|
|
|
++/* Enable the DFG JIT on MIPS. */
|
|
|
++#if CPU(MIPS)
|
|
|
++#define ENABLE_DFG_JIT 1
|
|
|
++#endif
|
|
|
+ #endif
|
|
|
+
|
|
|
+ /* If the jit is not available, enable the LLInt C Loop: */
|
|
|
+--
|
|
|
+1.8.3.2
|
|
|
+
|
Markos Chandras