configs/andes_ae300: remove defconfig

As we're about to remove the nds32 architecture support, remove the
only defconfig that used this CPU architecture.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>

DEVELOPERS

@@ -2174,7 +2174,6 @@ F:	package/tcf-agent/
 N:	Yu Chien Peter Lin <peterlin@andestech.com>
 F:	arch/Config.in.nds32
 F:	board/andes
-F:	configs/andes_ae300_defconfig
 F:	configs/andes_ae350_45_defconfig
 F:	toolchain/toolchain-external/toolchain-external-andes-nds32/
 

board/andes/ae300/ae300.fragment

@@ -1 +0,0 @@
-CONFIG_NDS32_BUILTIN_DTB="ae3xx"

board/andes/ae300/patches/linux/0001-nds32-Fix-boot-messages-garbled.patch

@@ -1,28 +0,0 @@
-From 90d52d180dcc5d1300dc352ca709eb6453894143 Mon Sep 17 00:00:00 2001
-From: Nylon Chen <nylon7@andestech.com>
-Date: Wed, 28 Nov 2018 16:26:46 +0800
-Subject: [PATCH] nds32: Fix boot messages garbled
-
-In order to display uart correctly we have to pass the correct setting of uart to kernel by bootarg.
-This patch will provide such settings to set the correct uart baud rate.
-
-Signed-off-by: Nylon Chen <nylon7@andestech.com>
----
- arch/nds32/boot/dts/ae3xx.dts | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
-index bb39749a6673..aefe2090926a 100644
---- a/arch/nds32/boot/dts/ae3xx.dts
-+++ b/arch/nds32/boot/dts/ae3xx.dts
-@@ -6,6 +6,7 @@
- 	interrupt-parent = <&intc>;
- 
- 	chosen {
-+		bootargs = "memblock=debug earlycon console=ttyS0,38400n8 debug loglevel=7";
- 		stdout-path = &serial0;
- 	};
- 
--- 
-2.18.0
-

board/andes/ae300/patches/linux/0002-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch

@@ -1,52 +0,0 @@
-From f9df4186c17d686f1ca38f973d7a3a49e8e37c01 Mon Sep 17 00:00:00 2001
-From: Dirk Mueller <dmueller@suse.com>
-Date: Tue, 14 Jan 2020 18:53:41 +0100
-Subject: [PATCH] scripts/dtc: Remove redundant YYLOC global declaration
-
-gcc 10 will default to -fno-common, which causes this error at link
-time:
-
-  (.text+0x0): multiple definition of `yylloc'; dtc-lexer.lex.o (symbol from plugin):(.text+0x0): first defined here
-
-This is because both dtc-lexer as well as dtc-parser define the same
-global symbol yyloc. Before with -fcommon those were merged into one
-defintion. The proper solution would be to to mark this as "extern",
-however that leads to:
-
-  dtc-lexer.l:26:16: error: redundant redeclaration of 'yylloc' [-Werror=redundant-decls]
-   26 | extern YYLTYPE yylloc;
-      |                ^~~~~~
-In file included from dtc-lexer.l:24:
-dtc-parser.tab.h:127:16: note: previous declaration of 'yylloc' was here
-  127 | extern YYLTYPE yylloc;
-      |                ^~~~~~
-cc1: all warnings being treated as errors
-
-which means the declaration is completely redundant and can just be
-dropped.
-
-Signed-off-by: Dirk Mueller <dmueller@suse.com>
-Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
-[robh: cherry-pick from upstream]
-Cc: stable@vger.kernel.org
-Signed-off-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
----
- scripts/dtc/dtc-lexer.l | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
-index 06c040902444..d1b3810156c7 100644
---- a/scripts/dtc/dtc-lexer.l
-+++ b/scripts/dtc/dtc-lexer.l
-@@ -38,7 +38,6 @@ LINECOMMENT	"//".*\n
- #include "srcpos.h"
- #include "dtc-parser.tab.h"
- 
--YYLTYPE yylloc;
- extern bool treesource_error;
- 
- /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
--- 
-2.25.1
-

board/andes/ae300/readme.txt

@@ -1,49 +0,0 @@
-Intro
-=====
-
-Andestech(nds32) AE300 Platform
-
-The AE300 prototype demonstrates the AE300 example platform on the FPGA.
-It is composed of one Andestech(nds32) processor and AE300.
-
-How to build it
-===============
-
-Configure Buildroot
--------------------
-
-The andes_ae300_defconfig configuration is a sample configuration with
-all that is required to bring the FPGA Development Board:
-
-  $ make andes_ae300_defconfig
-
-Build everything
-----------------
-Note: you will need to have access to the network, since Buildroot will
-download the packages' sources.
-
-  $ make
-
-Result of the build
--------------------
-
-After building, you should obtain this tree:
-
-output/images/
-    +-- vmlinux
-    +-- rootfs.cpio
-    +-- rootfs.tar
-
-How to run it
-=============
-
-Run
----
-
-  Setup the Console with the rate 38400/8-N-1.
-
-  $ cd output/images
-  $ ../host/bin/nds32le-linux-gdb vmlinux
-  $ target remote [your host]
-  $ lo
-  $ c 

configs/andes_ae300_defconfig

@@ -1,10 +0,0 @@
-BR2_nds32=y
-BR2_GLOBAL_PATCH_DIR="board/andes/ae300/patches"
-BR2_TOOLCHAIN_EXTERNAL=y
-BR2_TOOLCHAIN_EXTERNAL_ANDES_NDS32=y
-BR2_LINUX_KERNEL=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.17"
-BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y
-BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="board/andes/ae300/ae300.fragment"
-BR2_TARGET_ROOTFS_INITRAMFS=y