board/spike/riscv64/readme.txt: remove obsolete comment

At the time the spike_riscv64_defconfig was introduced in commit [1], it
was not possible to have a console input using Spike and OpenSBI for
RISC-V 32 bits. This limitation no longer applies, as upstream
components now implements support for this.

Buildroot commit [2] updated riscv-isa-sim (Spike), which now includes a
NS16550 uart emulation. This can be used by RV32 Linux Kernel. Finally,
a spike_riscv32_defconfig was added in [3].

This commit removes the comment about this limitation, since it no
longer applies.

[1] https://gitlab.com/buildroot.org/buildroot/-/commit/24d07fdc1404901fb1872ac55f875fe1d555cbb3
[2] https://gitlab.com/buildroot.org/buildroot/-/commit/853b7661bf5ddca5d4b81964ef1a19a133beac85
[3] https://gitlab.com/buildroot.org/buildroot/-/commit/a83ab3f4c8621dec58dc78a8dcb48e519377ac3d

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>

board/spike/riscv64/readme.txt

@@ -20,11 +20,6 @@ The boot is made with the standard RISC-V OpenSBI boot loader. In
 order to keep the simulation simple, the rootfs is passed as an initrd
 ramfs.
 
-Note: at the time of this writing, Spike v1.1.0 and OpenSBI v1.0 does
-not support console input emulation for 32bit RISC-V systems. A 32bit
-Linux system can boot and reach the login, but it's not possible to
-login. See [4].
-
 
 [1].
 https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#simulating-a-new-instruction
@@ -34,6 +29,3 @@ https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#debugging-with-g
 
 [3].
 https://github.com/riscv/riscv-openocd
-
-[4].
-https://github.com/riscv-software-src/opensbi/blob/v1.0/lib/utils/sys/htif.c#L127