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arch: tidy up mmu config

Instead of blacklisting which architectures support MMUs (mandatorily
or optionally), introduce two Kconfig options that are selected by each
architecture in each case.

This simplifies the logic in BR2_USE_MMU.

Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar>
Acked-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Guido Martínez 10 years ago
parent
80b91a21d3
commit
29563047e0
4 changed files with 49 additions and 2 deletions
Unified View Show Diff Stats
  1. 28 0
      arch/Config.in
  2. 17 0
      arch/Config.in.arm
  3. 2 0
      arch/Config.in.xtensa
  4. 2 2
      toolchain/toolchain-common.in

+ 28 - 0
arch/Config.in
View File 

@@ -9,6 +9,12 @@ config BR2_KERNEL_64_USERLAND_32
 
 config BR2_SOFT_FLOAT
 
 config BR2_SOFT_FLOAT
 
 	bool
 
 	bool
 
 
 
+config BR2_ARCH_HAS_MMU_MANDATORY
 
+	bool
 
+
 
+config BR2_ARCH_HAS_MMU_OPTIONAL
 
+	bool
 
+
 
 choice
 
 choice
 
 	prompt "Target Architecture"
 
 	prompt "Target Architecture"
 
 	default BR2_i386
 
 	default BR2_i386
 
@@ -17,6 +23,7 @@ choice
 
 
 
 config BR2_arcle
 
 config BR2_arcle
 
 	bool "ARC (little endian)"
 
 	bool "ARC (little endian)"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
 
 	  Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
 
 	  that can be used from deeply embedded to high performance host
 
 	  that can be used from deeply embedded to high performance host
 
@@ -24,6 +31,7 @@ config BR2_arcle
 
 
 
 config BR2_arceb
 
 config BR2_arceb
 
 	bool "ARC (big endian)"
 
 	bool "ARC (big endian)"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
 
 	  Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
 
 	  that can be used from deeply embedded to high performance host
 
 	  that can be used from deeply embedded to high performance host
 
@@ -31,6 +39,7 @@ config BR2_arceb
 
 
 
 config BR2_arm
 
 config BR2_arm
 
 	bool "ARM (little endian)"
 
 	bool "ARM (little endian)"
 
+	# MMU support is set by the subarchitecture file, arch/Config.in.arm
 
 	help
 
 	help
 
 	  ARM is a 32-bit reduced instruction set computer (RISC) instruction
 
 	  ARM is a 32-bit reduced instruction set computer (RISC) instruction
 
 	  set architecture (ISA) developed by ARM Holdings. Little endian.
 
 	  set architecture (ISA) developed by ARM Holdings. Little endian.
 
@@ -39,6 +48,7 @@ config BR2_arm
 
 
 
 config BR2_armeb
 
 config BR2_armeb
 
 	bool "ARM (big endian)"
 
 	bool "ARM (big endian)"
 
+	# MMU support is set by the subarchitecture file, arch/Config.in.arm
 
 	help
 
 	help
 
 	  ARM is a 32-bit reduced instruction set computer (RISC) instruction
 
 	  ARM is a 32-bit reduced instruction set computer (RISC) instruction
 
 	  set architecture (ISA) developed by ARM Holdings. Big endian.
 
 	  set architecture (ISA) developed by ARM Holdings. Big endian.
 
@@ -48,6 +58,7 @@ config BR2_armeb
 
 config BR2_aarch64
 
 config BR2_aarch64
 
 	bool "AArch64"
 
 	bool "AArch64"
 
 	select BR2_ARCH_IS_64
 
 	select BR2_ARCH_IS_64
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  Aarch64 is a 64-bit architecture developed by ARM Holdings.
 
 	  Aarch64 is a 64-bit architecture developed by ARM Holdings.
 
 	  http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
 
 	  http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
 
@@ -63,12 +74,14 @@ config BR2_bfin
 
 
 
 config BR2_i386
 
 config BR2_i386
 
 	bool "i386"
 
 	bool "i386"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  Intel i386 architecture compatible microprocessor
 
 	  Intel i386 architecture compatible microprocessor
 
 	  http://en.wikipedia.org/wiki/I386
 
 	  http://en.wikipedia.org/wiki/I386
 
 
 
 config BR2_m68k
 
 config BR2_m68k
 
 	bool "m68k"
 
 	bool "m68k"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	depends on BROKEN # ice in uclibc / inet_ntoa_r
 
 	depends on BROKEN # ice in uclibc / inet_ntoa_r
 
 	help
 
 	help
 
 	  Motorola 68000 family microprocessor
 
 	  Motorola 68000 family microprocessor
 
@@ -76,6 +89,7 @@ config BR2_m68k
 
 
 
 config BR2_microblazeel
 
 config BR2_microblazeel
 
 	bool "Microblaze AXI (little endian)"
 
 	bool "Microblaze AXI (little endian)"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
 
 	  Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
 
 	  based architecture (little endian)
 
 	  based architecture (little endian)
 
@@ -84,6 +98,7 @@ config BR2_microblazeel
 
 
 
 config BR2_microblazebe
 
 config BR2_microblazebe
 
 	bool "Microblaze non-AXI (big endian)"
 
 	bool "Microblaze non-AXI (big endian)"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
 
 	  Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
 
 	  based architecture (non-AXI, big endian)
 
 	  based architecture (non-AXI, big endian)
 
@@ -92,6 +107,7 @@ config BR2_microblazebe
 
 
 
 config BR2_mips
 
 config BR2_mips
 
 	bool "MIPS (big endian)"
 
 	bool "MIPS (big endian)"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
 
 	  MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
 
 	  http://www.mips.com/
 
 	  http://www.mips.com/
 
@@ -99,6 +115,7 @@ config BR2_mips
 
 
 
 config BR2_mipsel
 
 config BR2_mipsel
 
 	bool "MIPS (little endian)"
 
 	bool "MIPS (little endian)"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
 
 	  MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
 
 	  http://www.mips.com/
 
 	  http://www.mips.com/
 
@@ -107,6 +124,7 @@ config BR2_mipsel
 
 config BR2_mips64
 
 config BR2_mips64
 
 	bool "MIPS64 (big endian)"
 
 	bool "MIPS64 (big endian)"
 
 	select BR2_ARCH_IS_64
 
 	select BR2_ARCH_IS_64
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
 
 	  MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
 
 	  http://www.mips.com/
 
 	  http://www.mips.com/
 
@@ -115,6 +133,7 @@ config BR2_mips64
 
 config BR2_mips64el
 
 config BR2_mips64el
 
 	bool "MIPS64 (little endian)"
 
 	bool "MIPS64 (little endian)"
 
 	select BR2_ARCH_IS_64
 
 	select BR2_ARCH_IS_64
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
 
 	  MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
 
 	  http://www.mips.com/
 
 	  http://www.mips.com/
 
@@ -122,6 +141,7 @@ config BR2_mips64el
 
 
 
 config BR2_nios2
 
 config BR2_nios2
 
 	bool "Nios II"
 
 	bool "Nios II"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  Nios II is a soft core processor from Altera Corporation.
 
 	  Nios II is a soft core processor from Altera Corporation.
 
 	  http://www.altera.com/
 
 	  http://www.altera.com/
 
@@ -129,6 +149,7 @@ config BR2_nios2
 
 
 
 config BR2_powerpc
 
 config BR2_powerpc
 
 	bool "PowerPC"
 
 	bool "PowerPC"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
 
 	  PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
 
 	  Big endian.
 
 	  Big endian.
 
@@ -138,6 +159,7 @@ config BR2_powerpc
 
 config BR2_powerpc64
 
 config BR2_powerpc64
 
 	bool "PowerPC64 (big endian)"
 
 	bool "PowerPC64 (big endian)"
 
 	select BR2_ARCH_IS_64
 
 	select BR2_ARCH_IS_64
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
 
 	  PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
 
 	  Big endian.
 
 	  Big endian.
 
@@ -147,6 +169,7 @@ config BR2_powerpc64
 
 config BR2_powerpc64le
 
 config BR2_powerpc64le
 
 	bool "PowerPC64 (little endian)"
 
 	bool "PowerPC64 (little endian)"
 
 	select BR2_ARCH_IS_64
 
 	select BR2_ARCH_IS_64
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
 
 	  PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
 
 	  Little endian.
 
 	  Little endian.
 
@@ -155,6 +178,7 @@ config BR2_powerpc64le
 
 
 
 config BR2_sh
 
 config BR2_sh
 
 	bool "SuperH"
 
 	bool "SuperH"
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 	help
 
 	help
 
 	  SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
 
 	  SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
 
 	  instruction set architecture (ISA) developed by Hitachi.
 
 	  instruction set architecture (ISA) developed by Hitachi.
 
@@ -164,6 +188,7 @@ config BR2_sh
 
 config BR2_sh64
 
 config BR2_sh64
 
 	bool "SuperH64"
 
 	bool "SuperH64"
 
 	depends on BR2_DEPRECATED_SINCE_2015_05
 
 	depends on BR2_DEPRECATED_SINCE_2015_05
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
 
 	  SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
 
 	  instruction set architecture (ISA) developed by Hitachi.
 
 	  instruction set architecture (ISA) developed by Hitachi.
 
@@ -172,6 +197,7 @@ config BR2_sh64
 
 
 
 config BR2_sparc
 
 config BR2_sparc
 
 	bool "SPARC"
 
 	bool "SPARC"
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  SPARC (from Scalable Processor Architecture) is a RISC instruction
 
 	  SPARC (from Scalable Processor Architecture) is a RISC instruction
 
 	  set architecture (ISA) developed by Sun Microsystems.
 
 	  set architecture (ISA) developed by Sun Microsystems.
 
@@ -181,6 +207,7 @@ config BR2_sparc
 
 config BR2_x86_64
 
 config BR2_x86_64
 
 	bool "x86_64"
 
 	bool "x86_64"
 
 	select BR2_ARCH_IS_64
 
 	select BR2_ARCH_IS_64
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  x86-64 is an extension of the x86 instruction set (Intel i386
 
 	  x86-64 is an extension of the x86 instruction set (Intel i386
 
 	  architecture compatible microprocessor).
 
 	  architecture compatible microprocessor).
 
@@ -188,6 +215,7 @@ config BR2_x86_64
 
 
 
 config BR2_xtensa
 
 config BR2_xtensa
 
 	bool "Xtensa"
 
 	bool "Xtensa"
 
+	# MMU support is set by the subarchitecture file, arch/Config.in.xtensa
 
 	help
 
 	help
 
 	  Xtensa is a Tensilica processor IP architecture.
 
 	  Xtensa is a Tensilica processor IP architecture.
 
 	  http://en.wikipedia.org/wiki/Xtensa
 
 	  http://en.wikipedia.org/wiki/Xtensa

+ 17 - 0
arch/Config.in.arm
View File 

@@ -64,34 +64,40 @@ config BR2_arm920t
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_ARMV4
 
 	select BR2_ARM_CPU_ARMV4
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_arm922t
 
 config BR2_arm922t
 
 	bool "arm922t"
 
 	bool "arm922t"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_ARMV4
 
 	select BR2_ARM_CPU_ARMV4
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_arm926t
 
 config BR2_arm926t
 
 	bool "arm926t"
 
 	bool "arm926t"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_MAYBE_HAS_VFPV2
 
 	select BR2_ARM_CPU_MAYBE_HAS_VFPV2
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_ARMV5
 
 	select BR2_ARM_CPU_ARMV5
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_arm1136jf_s
 
 config BR2_arm1136jf_s
 
 	bool "arm1136jf-s"
 
 	bool "arm1136jf-s"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_VFPV2
 
 	select BR2_ARM_CPU_HAS_VFPV2
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_ARMV6
 
 	select BR2_ARM_CPU_ARMV6
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_arm1176jz_s
 
 config BR2_arm1176jz_s
 
 	bool "arm1176jz-s"
 
 	bool "arm1176jz-s"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_ARMV6
 
 	select BR2_ARM_CPU_ARMV6
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_arm1176jzf_s
 
 config BR2_arm1176jzf_s
 
 	bool "arm1176jzf-s"
 
 	bool "arm1176jzf-s"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_VFPV2
 
 	select BR2_ARM_CPU_HAS_VFPV2
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_ARMV6
 
 	select BR2_ARM_CPU_ARMV6
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_cortex_a5
 
 config BR2_cortex_a5
 
 	bool "cortex-A5"
 
 	bool "cortex-A5"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
@@ -99,6 +105,7 @@ config BR2_cortex_a5
 
 	select BR2_ARM_CPU_MAYBE_HAS_VFPV4
 
 	select BR2_ARM_CPU_MAYBE_HAS_VFPV4
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_ARMV7A
 
 	select BR2_ARM_CPU_ARMV7A
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_cortex_a7
 
 config BR2_cortex_a7
 
 	bool "cortex-A7"
 
 	bool "cortex-A7"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
@@ -106,6 +113,7 @@ config BR2_cortex_a7
 
 	select BR2_ARM_CPU_HAS_VFPV4
 
 	select BR2_ARM_CPU_HAS_VFPV4
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_ARMV7A
 
 	select BR2_ARM_CPU_ARMV7A
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_cortex_a8
 
 config BR2_cortex_a8
 
 	bool "cortex-A8"
 
 	bool "cortex-A8"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
@@ -113,6 +121,7 @@ config BR2_cortex_a8
 
 	select BR2_ARM_CPU_HAS_VFPV3
 
 	select BR2_ARM_CPU_HAS_VFPV3
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_ARMV7A
 
 	select BR2_ARM_CPU_ARMV7A
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_cortex_a9
 
 config BR2_cortex_a9
 
 	bool "cortex-A9"
 
 	bool "cortex-A9"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
@@ -120,6 +129,7 @@ config BR2_cortex_a9
 
 	select BR2_ARM_CPU_MAYBE_HAS_VFPV3
 
 	select BR2_ARM_CPU_MAYBE_HAS_VFPV3
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_ARMV7A
 
 	select BR2_ARM_CPU_ARMV7A
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_cortex_a12
 
 config BR2_cortex_a12
 
 	bool "cortex-A12"
 
 	bool "cortex-A12"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
@@ -127,6 +137,7 @@ config BR2_cortex_a12
 
 	select BR2_ARM_CPU_HAS_VFPV4
 
 	select BR2_ARM_CPU_HAS_VFPV4
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_ARMV7A
 
 	select BR2_ARM_CPU_ARMV7A
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_cortex_a15
 
 config BR2_cortex_a15
 
 	bool "cortex-A15"
 
 	bool "cortex-A15"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
@@ -134,28 +145,34 @@ config BR2_cortex_a15
 
 	select BR2_ARM_CPU_HAS_VFPV4
 
 	select BR2_ARM_CPU_HAS_VFPV4
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_HAS_THUMB2
 
 	select BR2_ARM_CPU_ARMV7A
 
 	select BR2_ARM_CPU_ARMV7A
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_fa526
 
 config BR2_fa526
 
 	bool "fa526/626"
 
 	bool "fa526/626"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_ARMV4
 
 	select BR2_ARM_CPU_ARMV4
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_pj4
 
 config BR2_pj4
 
 	bool "pj4"
 
 	bool "pj4"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_VFPV3
 
 	select BR2_ARM_CPU_HAS_VFPV3
 
 	select BR2_ARM_CPU_ARMV7A
 
 	select BR2_ARM_CPU_ARMV7A
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_strongarm
 
 config BR2_strongarm
 
 	bool "strongarm sa110/sa1100"
 
 	bool "strongarm sa110/sa1100"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_ARMV4
 
 	select BR2_ARM_CPU_ARMV4
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_xscale
 
 config BR2_xscale
 
 	bool "xscale"
 
 	bool "xscale"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_HAS_THUMB
 
 	select BR2_ARM_CPU_ARMV5
 
 	select BR2_ARM_CPU_ARMV5
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 config BR2_iwmmxt
 
 config BR2_iwmmxt
 
 	bool "iwmmxt"
 
 	bool "iwmmxt"
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_HAS_ARM
 
 	select BR2_ARM_CPU_ARMV5
 
 	select BR2_ARM_CPU_ARMV5
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 endchoice
 
 endchoice
 
 
 
 choice
 
 choice

+ 2 - 0
arch/Config.in.xtensa
View File 

@@ -3,8 +3,10 @@ choice
 
 	depends on BR2_xtensa
 
 	depends on BR2_xtensa
 
 	default BR2_xtensa_fsf
 
 	default BR2_xtensa_fsf
 
 config BR2_XTENSA_CUSTOM
 
 config BR2_XTENSA_CUSTOM
 
+	select BR2_ARCH_HAS_MMU_OPTIONAL
 
 	bool "Custom Xtensa processor configuration"
 
 	bool "Custom Xtensa processor configuration"
 
 config BR2_xtensa_fsf
 
 config BR2_xtensa_fsf
 
+	select BR2_ARCH_HAS_MMU_MANDATORY
 
 	bool "fsf - Default configuration"
 
 	bool "fsf - Default configuration"
 
 endchoice
 
 endchoice

+ 2 - 2
toolchain/toolchain-common.in
View File 

@@ -108,8 +108,8 @@ config BR2_NEEDS_GETTEXT_IF_LOCALE
 
 	default y if (BR2_NEEDS_GETTEXT && BR2_ENABLE_LOCALE)
 
 	default y if (BR2_NEEDS_GETTEXT && BR2_ENABLE_LOCALE)
 
 
 
 config BR2_USE_MMU
 
 config BR2_USE_MMU
 
-	bool "Enable MMU support" if BR2_arm || BR2_armeb || BR2_sh || BR2_xtensa
 
-	default y if !BR2_bfin
 
+	bool "Enable MMU support" if BR2_ARCH_HAS_MMU_OPTIONAL
 
+	default y if BR2_ARCH_HAS_MMU_OPTIONAL || BR2_ARCH_HAS_MMU_MANDATORY
 
 	help
 
 	help
 
 	  If your target has a MMU, you should say Y here.  If you
 
 	  If your target has a MMU, you should say Y here.  If you
 
 	  are unsure, just say Y.
 
 	  are unsure, just say Y.