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configs/spike_riscv64: new defconfig

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Julien Olivain 3 년 전
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4개의 변경된 파일67개의 추가작업 그리고 0개의 파일을 삭제
  1. 2 0
      DEVELOPERS
  2. 39 0
      board/spike/riscv64/readme.txt
  3. 13 0
      board/spike/riscv64/start.sh
  4. 13 0
      configs/spike_riscv64_defconfig

+ 2 - 0
DEVELOPERS

@@ -1588,10 +1588,12 @@ F:	package/paho-mqtt-c
 
 N:	Julien Olivain <ju.o@free.fr>
 F:	board/qmtech/zynq/
+F:	board/spike/
 F:	board/technexion/imx8mmpico/
 F:	board/technexion/imx8mpico/
 F:	configs/imx8mmpico_defconfig
 F:	configs/imx8mpico_defconfig
+F:	configs/spike_riscv64_defconfig
 F:	configs/zynq_qmtech_defconfig
 F:	package/fluid-soundfont/
 F:	package/fluidsynth/

+ 39 - 0
board/spike/riscv64/readme.txt

@@ -0,0 +1,39 @@
+Linux on Spike RISC-V ISA simulator
+===================================
+
+This configuration provides a minimal working setup to run a Linux
+kernel in the Spike RISC-V ISA simulator.
+
+The Spike ISA simulator can be an interresting alternative to Qemu, in
+some specific cases. For example: simulating new instructions (see [1]),
+simulating riscv-openocd/gdb debug sessions (see [2], [3]), or
+generating an accurate per-instruction log of execution (see
+riscv-isa-sim spike -l option)...
+
+To run Buildroot Linux in Spike, use the commands:
+
+    make spike_riscv64_defconfig
+    make
+    ./board/spike/riscv64/start.sh
+
+The boot is made with the standard RISC-V OpenSBI boot loader. In
+order to keep the simulation simple, the rootfs is passed as an initrd
+ramfs.
+
+Note: at the time of this writing, Spike v1.1.0 and OpenSBI v1.0 does
+not support console input emulation for 32bit RISC-V systems. A 32bit
+Linux system can boot and reach the login, but it's not possible to
+login. See [4].
+
+
+[1].
+https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#simulating-a-new-instruction
+
+[2].
+https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#debugging-with-gdb
+
+[3].
+https://github.com/riscv/riscv-openocd
+
+[4].
+https://github.com/riscv-software-src/opensbi/blob/v1.0/lib/utils/sys/htif.c#L127

+ 13 - 0
board/spike/riscv64/start.sh

@@ -0,0 +1,13 @@
+#! /bin/sh
+
+SCRIPT_DIR="$(dirname "$0")"
+BR_BASEDIR="$(readlink -e "${SCRIPT_DIR}/../../..")"
+
+# Use Buildroot host spike by default, but allow the caller to
+# redefine another spike binary
+: "${SPIKE:=${BR_BASEDIR}/output/host/usr/bin/spike}"
+
+exec "${SPIKE}" \
+    --initrd "${BR_BASEDIR}"/output/images/rootfs.cpio \
+    "${@}" \
+    "${BR_BASEDIR}"/output/images/fw_payload.elf

+ 13 - 0
configs/spike_riscv64_defconfig

@@ -0,0 +1,13 @@
+BR2_riscv=y
+BR2_RISCV_64=y
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.15.13"
+BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_15=y
+BR2_TARGET_ROOTFS_CPIO=y
+# BR2_TARGET_ROOTFS_TAR is not set
+BR2_TARGET_OPENSBI=y
+BR2_TARGET_OPENSBI_PLAT="generic"
+BR2_TARGET_OPENSBI_LINUX_PAYLOAD=y
+BR2_PACKAGE_HOST_RISCV_ISA_SIM=y