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@@ -0,0 +1,199 @@
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+diff -Naur a/board/ti/am335x/board.c b/board/ti/am335x/board.c
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+--- a/board/ti/am335x/board.c 2013-10-16 19:08:12.000000000 +0200
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++++ b/board/ti/am335x/board.c 2017-10-14 15:42:36.164008177 +0200
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+@@ -76,6 +76,14 @@
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+ }
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+ }
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+
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++ puts("BOARD EEPROMID : ");
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++ {
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++ char cc[HDR_NAME_LEN + 1];
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++ memset(cc, 0, sizeof(cc));
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++ memcpy(cc, header->name, HDR_NAME_LEN);
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++ puts(cc);
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++ }
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++ puts("\n");
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+ return 0;
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+ }
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+
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+@@ -148,6 +156,14 @@
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+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
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+ };
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+
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++static const struct ddr_data ddr3_beaglepocket_data = {
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++ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
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++ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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++ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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++ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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++ .datadldiff0 = PHY_DLL_LOCK_DIFF,
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++};
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++
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+ static const struct ddr_data ddr3_evm_data = {
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+ .datardsratio0 = MT41J512M8RH125_RD_DQS,
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+ .datawdsratio0 = MT41J512M8RH125_WR_DQS,
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+@@ -184,6 +200,20 @@
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+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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+ };
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+
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++static const struct cmd_control ddr3_beaglepocket_cmd_ctrl_data = {
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++ .cmd0csratio = MT41K256M16HA125E_RATIO,
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++ .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
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++ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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++
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++ .cmd1csratio = MT41K256M16HA125E_RATIO,
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++ .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
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++ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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++
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++ .cmd2csratio = MT41K256M16HA125E_RATIO,
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++ .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
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++ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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++};
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++
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+ static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
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+ .cmd0csratio = MT41J512M8RH125_RATIO,
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+ .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
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+@@ -219,6 +249,16 @@
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+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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+ };
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+
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++static struct emif_regs ddr3_beaglepocket_emif_reg_data = {
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++ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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++ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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++ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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++ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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++ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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++ .zq_config = MT41K256M16HA125E_ZQ_CFG,
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++ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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++};
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++
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+ static struct emif_regs ddr3_evm_emif_reg_data = {
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+ .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
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+ .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
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+@@ -245,6 +285,8 @@
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+ 303, OSC-1, 1, -1, -1, -1, -1};
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+ const struct dpll_params dpll_ddr_bone_black = {
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+ 400, OSC-1, 1, -1, -1, -1, -1};
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++const struct dpll_params dpll_ddr_bone_pocket = {
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++ 400, OSC-1, 1, -1, -1, -1, -1};
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+
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+ void am33xx_spl_board_init(void)
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+ {
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+@@ -257,7 +299,8 @@
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+ /* Get the frequency */
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+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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+
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+- if (board_is_bone(&header) || board_is_bone_lt(&header)) {
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++ if (board_is_bone(&header) || board_is_bone_lt(&header) ||
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++ board_is_bone_pocket(&header)) {
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+ /* BeagleBone PMIC Code */
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+ int usb_cur_lim;
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+
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+@@ -291,7 +334,7 @@
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+ * Override what we have detected since we know if we have
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+ * a Beaglebone Black it supports 1GHz.
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+ */
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+- if (board_is_bone_lt(&header))
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++ if (board_is_bone_lt(&header) || board_is_bone_pocket(&header))
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+ dpll_mpu_opp100.m = MPUPLL_M_1000;
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+
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+ /*
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+@@ -403,6 +446,8 @@
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+ return &dpll_ddr_evm_sk;
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+ else if (board_is_bone_lt(&header))
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+ return &dpll_ddr_bone_black;
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++ else if (board_is_bone_pocket(&header))
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++ return &dpll_ddr_bone_pocket;
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+ else if (board_is_evm_15_or_later(&header))
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+ return &dpll_ddr_evm_sk;
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+ else
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+@@ -465,6 +510,11 @@
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+ &ddr3_beagleblack_data,
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+ &ddr3_beagleblack_cmd_ctrl_data,
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+ &ddr3_beagleblack_emif_reg_data, 0);
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++ else if (board_is_bone_pocket(&header))
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++ config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
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++ &ddr3_beaglepocket_data,
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++ &ddr3_beaglepocket_cmd_ctrl_data,
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++ &ddr3_beaglepocket_emif_reg_data, 0);
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+ else if (board_is_evm_15_or_later(&header))
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+ config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
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+ &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
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+@@ -597,7 +647,7 @@
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+ puts("Could not get board ID.\n");
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+
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+ if (board_is_bone(&header) || board_is_bone_lt(&header) ||
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+- board_is_idk(&header)) {
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++ board_is_idk(&header) || board_is_bone_pocket(&header)) {
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+ writel(MII_MODE_ENABLE, &cdev->miisel);
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+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
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+ PHY_INTERFACE_MODE_MII;
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+diff -Naur a/board/ti/am335x/board.h b/board/ti/am335x/board.h
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+--- a/board/ti/am335x/board.h 2013-10-16 19:08:12.000000000 +0200
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++++ b/board/ti/am335x/board.h 2017-10-14 15:30:35.318501215 +0200
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+@@ -36,7 +36,12 @@
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+
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+ static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
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+ {
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+- return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
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++ return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
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++}
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++
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++static inline int board_is_bone_pocket(struct am335x_baseboard_id *header)
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++{
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++ return !strncmp(header->name, "A335PBGL", HDR_NAME_LEN);
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+ }
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+
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+ static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
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+diff -Naur a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
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+--- a/board/ti/am335x/mux.c 2013-10-16 19:08:12.000000000 +0200
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++++ b/board/ti/am335x/mux.c 2017-10-14 15:24:51.513779688 +0200
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+@@ -333,6 +333,7 @@
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+ /* Do board-specific muxes. */
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+ if (board_is_bone(header)) {
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+ /* Beaglebone pinmux */
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++ puts("is_bone setup\n");
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+ configure_module_pin_mux(i2c1_pin_mux);
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+ configure_module_pin_mux(mii1_pin_mux);
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+ configure_module_pin_mux(mmc0_pin_mux);
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+@@ -344,6 +345,7 @@
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+ #endif
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+ } else if (board_is_gp_evm(header)) {
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+ /* General Purpose EVM */
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++ puts("is_gp_evm setup\n");
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+ unsigned short profile = detect_daughter_board_profile();
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+ configure_module_pin_mux(rgmii1_pin_mux);
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+ configure_module_pin_mux(mmc0_pin_mux);
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+@@ -364,22 +366,32 @@
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+ * So u-boot mus be build with CONFIG_SERIAL4 and
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+ * CONFIG_CONS_INDEX=4
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+ */
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++ puts("is_idk setup\n");
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+ configure_module_pin_mux(mii1_pin_mux);
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+ configure_module_pin_mux(mmc0_no_cd_pin_mux);
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+ } else if (board_is_evm_sk(header)) {
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+ /* Starter Kit EVM */
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++ puts("is_evm_sk setup\n");
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+ configure_module_pin_mux(i2c1_pin_mux);
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+ configure_module_pin_mux(gpio0_7_pin_mux);
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+ configure_module_pin_mux(rgmii1_pin_mux);
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+ configure_module_pin_mux(mmc0_pin_mux_sk_evm);
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+ } else if (board_is_bone_lt(header)) {
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+ /* Beaglebone LT pinmux */
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++ puts("is_bone_lt setup\n");
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++ configure_module_pin_mux(i2c1_pin_mux);
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++ configure_module_pin_mux(mii1_pin_mux);
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++ configure_module_pin_mux(mmc0_pin_mux);
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++ configure_module_pin_mux(mmc1_pin_mux);
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++ } else if (board_is_bone_pocket(header)) {
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++ /* Beaglebone pocket pinmux */
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++ puts("is_bone_pocket setup\n");
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+ configure_module_pin_mux(i2c1_pin_mux);
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+ configure_module_pin_mux(mii1_pin_mux);
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+ configure_module_pin_mux(mmc0_pin_mux);
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+ configure_module_pin_mux(mmc1_pin_mux);
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+ } else {
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+- puts("Unknown board, cannot configure pinmux.");
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++ puts("Unknown board, cannot configure pinmux.\n");
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+ hang();
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+ }
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+ }
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